integer-N PLL locking - please guide to debug

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dinesh agarwal

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integer n pll

my PLL designed for 2.475 GHZ is locked to 2.485Ghz

ref frequency is 5HHZ and divide ratio is 495.

please guide to debug
 

vco vtune signal

It seems to be an programming error ( LSB might be wrong loaded )..
 
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integer n pll +2009

the ratio control bits are checked and provide the ratio 495 correctly

any other possibility
 

Re: integer-N PLL locking

dinesh agarwal said:
my PLL designed for 2.475 GHZ is locked to 2.485Ghz

ref frequency is 5HHZ and divide ratio is 495.

please guide to debug
Click to expand...

Hi dinesh agarwal,

I'm facing the same problem with my PLL. I'm not sure about that but I think that the problem is related to the charge pump and leakage in the filter.

In fact suppose that your PLL feedback signal generate the UP of the CP and Reference signal generates the Down signal. When the PLL is locked, the average charge and decharge is zero. So, considering the leakage in the CP, the VCO Vtune will decrease. So the feedback signal must be a little bit higher in frequency in order to compensate the leakage loss.

Do anybody agree with me ?
 

Re: integer-N PLL locking

1st, is it really locked? ie. if you change the reference frequency a little, does the VCO frequency change EXACTLY how far the math says it should?

It is often a case that the PLL chip needs to be programmed in a odd way. Sometimes the N number is really N+1, or something like that. Read the data sheet carefully. If there is vendor supplied software, program that software and look at what IT tells you the register should read as.

Rich
www.MaguffinMicrowave.com
 

Re: integer-N PLL locking


No... No amount of leakage can create this error. It can manifest only as spur in the pnoise spectrum.
It must only be a case of misinterpreting the divide factor
 

Re: integer-N PLL locking

saro_k_82 said:
No... No amount of leakage can create this error. It can manifest only as spur in the pnoise spectrum.
It must only be a case of misinterpreting the divide factor
Click to expand...

As said, the frequency divider is perfect.
In my case it can perfectly divide frequencies below 10 GHz. I use it to divide a 2 GHz signal. The division is by 16 which is simple to implement (Divider is a cascade of 4 TSPC DFF based divide by 2).
That's why I deduced that he problem has no relation with the frequency divider.

@dinesh agarwal
Which technology are u using ?
 

Re: integer-N PLL locking

TSPC designed without the feedback inverters will have min frequency limit. More so for flops designed to work at 10GHz can fail at 500MHz in extreme cases.

It's just that I'm not able to find any other fault....
 

Re: integer-N PLL locking

Perhaps your reference osc has drifted.
 

integer-N PLL locking

If you program the divider ratio 490 that will give you "normally" 2450MHz, and also VCO frequency increases 5MHz with this programming, one can say that the programming works well...
Try this verification,then we discuss..
 

Re: integer-N PLL locking

Thers are other solutions to fix this bug like using a voltage offset to the VCO Vtune.

BigBoss said:
If you program the divider ratio 490 that will give you "normally" 2450MHz, and also VCO frequency increases 5MHz with this programming, one can say that the programming works well...
Try this verification,then we discuss..
Click to expand...

Yeah !
I totally agree with you Bigboss. So the best solution is to program the divider ratio to 494,493,492... if the Feedback generates the CP's Down signal and 496,497,498..500 if it generates the UP signal.

This solution is prety good only for PLL with high divider ratio which is not my case.

Can someone propose another solution ?
 

Re: integer-N PLL locking

Maybe your Fref is off (Extra Board Capacitance).
See if the Fref = 5.02MHz.
 

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