Instruction memory (Problem in VHDL)

[MAAASD]

Hello all,

Can you please help me to find what's wrong with this code?
i want to initialize the memory from file named "imem.txt"
it was supposed to initialize it from file named "imem.dat"
but i even don't know what is this file and how one could store the machine code in such files
so i replaced it by .txt file
is that possible?
could you tell me how to convert me MIPS assembly into machine code ? and how to put this machine code in a ".dat" file?
check this code
View attachment imem.zip

please i need your help
Thanks in advance!

 

[TrickyDicky]

I assume this is a testbench problem, because this code is not synthesisable.

But you dont say what the problem is - so what is the problem.

 

[MAAASD]

I assume this is a testbench problem, because this code is not synthesisable.

But you dont say what the problem is - so what is the problem.

I was thinking you would try to compile it
when i compile the code it sends the "Format error on line 0" to "Format error on line 63"
and
"Error (10384): VHDL assignment error at imem.vhd(46): index 64 is outside the range (63 downto 0) of object "mem"

and i have asked many questions i hope to know their answers
1) assume that you've written an assembly code
how would you get the machine code equivalent to it?
2) how to put it in a ".dat" file ?
3) can you initialize the memory from a ".txt" instead of ".dat" file?

 

[TrickyDicky]

There are 65 lines in your memory file. Remove the carrige return from the end of the file

 

[MAAASD]

There are 65 lines in your memory file. Remove the carrige return from the end of the file

i've made what you suggested but i got the same error
and i forget to tell you about this error
Error (10442): VHDL Process Statement error at imem.vhd(15): Process Statement must contain either a sensitivity list or a Wait Statement

 

[TrickyDicky]

Compiles and runs fine for me in modelsim.
Are you trying to compile it in quartus or ISE? Because this code cannot be compiled for an FPGA.

 

[MAAASD]

Compiles and runs fine for me in modelsim.
Are you trying to compile it in quartus or ISE? Because this code cannot be compiled for an FPGA.

yes i try to compile it on quartus, you suggest me to download modelsim?

and another question, how to convert my MIPS assembly language to machine code?
what to use?

 

[TrickyDicky]

yes i try to compile it on quartus, you suggest me to download modelsim?

What is your final goal? Modelsim is just a simulation tool. This code CANNOT be used on an FPGA - you will need to write different code if you want this to work on an FPGA.

and another question, how to convert my MIPS assembly language to machine code?
what to use?

I cannot answer that one.

 

[ads_ee]

and another question, how to convert my MIPS assembly language to machine code?
what to use?

I cannot answer that one.

How about using a MIPS Macro Assembler program. That's typically what would be used to convert an assembly language program to the equivalent machine code.

It's pretty obvious MAAASD that you are a high level software type that wants to dabble in FPGAs (because VHDL/Verilog is "code").

MAAASD, FYI, FPGAs are not software, VHDL/Verilog is not software. FPGAs are hardware with a design entry method that masquerades as software. You have to look at FPGA design as hardware design. Hence the reason so many here tout drawing a block diagram of the design before writing one line of "code". MAAASD learn how hardware works (learn about HW registers, combinatorial logic, setup/hold time, clocks, race conditions, metastability, sequential circuits, signaling standards, etc). Once you understand the difference between HW and SW, you'll have a starting point from which you can begin you first FPGA design.

Regards,
-alan

 

[MAAASD]

What is your final goal? Modelsim is just a simulation tool. This code CANNOT be used on an FPGA - you will need to write different code if you want this to work on an FPGA.



I cannot answer that one.

my goal is to make sure that, the implementation(the processor) is working on the simulation tool
then i can download it on an FGPA.

- - - Updated - - -

How about using a MIPS Macro Assembler program. That's typically what would be used to convert an assembly language program to the equivalent machine code.

It's pretty obvious MAAASD that you are a high level software type that wants to dabble in FPGAs (because VHDL/Verilog is "code").

MAAASD, FYI, FPGAs are not software, VHDL/Verilog is not software. FPGAs are hardware with a design entry method that masquerades as software. You have to look at FPGA design as hardware design. Hence the reason so many here tout drawing a block diagram of the design before writing one line of "code". MAAASD learn how hardware works (learn about HW registers, combinatorial logic, setup/hold time, clocks, race conditions, metastability, sequential circuits, signaling standards, etc). Once you understand the difference between HW and SW, you'll have a starting point from which you can begin you first FPGA design.

Regards,
-alan

I know what you said, VHDL is a hardware description language
my goal is to make a "Testbench" to test the design of a microprocessor on a simulation tool
then i can go through to download it to an FPGA

- - - Updated - - -

of course any advice is much appreciated
i wait for your reply

 

[TrickyDicky]

my goal is to make sure that, the implementation(the processor) is working on the simulation tool
then i can download it on an FGPA.

Ok, then download the simulator and stop trying to compile it in quartus - like I said, you cannot synthesise this code. It will need re-writing.

I know what you said, VHDL is a hardware description language
my goal is to make a "Testbench" to test the design of a microprocessor on a simulation tool
then i can go through to download it to an FPGA

Then I suggest you get started on a testbench.