instnciate a VHDL module into a verilog hierarchy help!!!!!!

Status
Not open for further replies.
H

hawk

Member level 4
Joined
Nov 27, 2001
Messages
76
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
384
Hi fox ,
Need your help ASAP to instanciate a vhdl module into a verilog
Hierarchy.
Please help how to do this.
Should i do this same as a regular verilog instanciation?????
Hawk.
 

Re: instnciate a VHDL module into a verilog hierarchy help!!

hawk said:
Hi fox ,
Need your help ASAP to instanciate a vhdl module into a verilog
Hierarchy.
Please help how to do this.
Should i do this same as a regular verilog instanciation?????
Hawk.
Click to expand...

Hello,

Read before the verilog source, the VHDL module can be instanciated....I think...

Good luck! :wink:
 

Hi

How should i instance the vhdl?
should i use vhdl syntax of instanciation in the verilog source ?
or should i use verilog syntax of instanciation of the vhdl module
in the verilog source ????
still need help.
regards,
hawk.
 

Re: Hi

hawk said:
How should i instance the vhdl?
should i use vhdl syntax of instanciation in the verilog source ?
or should i use verilog syntax of instanciation of the vhdl module
in the verilog source ????
still need help.
regards,
hawk.
Click to expand...

U have to instanciate the VHDL module like any other verilog module:

vhdl_module_name instance_name(port_instanciantion);

I hope this helps.
 

hi

This is not working.
still need help,
Hawk.
 

Re: hi

hawk said:
This is not working.
still need help,
Hawk.
Click to expand...

Well, depends on what synthesys tool u are using, I guess...

I use DC.

So, the order is to be like this:

-assume the the vhdl module is named link_core;
-in the verilog file, instanciate the module:
link_core instance_link_core(.input1(in1), ....);
-I read the vhdl file in which i wrote the code;
-I read the verilog file and link the design and it should work.....

If not, give more info, pls.

Regards....
 

Hi

Hi,
How should i do this in the simulation process not in the synth'??
I use nc sim.
how should i tell novas/NC to read it correctly?
Regards,
Hawk.
 

Hi

What do you meen for link the design???
in the simulation process.
Hawk.
 

Re: Hi

hawk said:
Hi,
How should i do this in the simulation process not in the synth'??
I use nc sim.
how should i tell novas/NC to read it correctly?
Regards,
Hawk.
Click to expand...

I'm not sure if nc sim reads verilog and vhdl together.....
I know ModelSim does that....
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…