instantiation with in an always block

[anusha vasanta]

Hi all,
is there any way to do the instantiation inside always block, here i had a code which had a tmp_reg first it should have one value and next it should take some other how could it be possible for this generate block

			genvar m;
			generate
			for(m=0;m<BLOCKS;m=m+1)
			begin :RAM4

			  assign   tmp_reg=mic_h2_result;
			  assign block_data[m]=data_new[(m*128)+127:(m*128)]; 
			  assign block_out[m]=(tmp_reg^block_data[m]);
			  Top_PipelinedCipher ROM4(clk,reset,data_valid_in,key_valid_in,key,block_out[m],valid_out,block_result[m]);
			  assign tmp_reg=block_result[m];
			end
			endgenerate

 

[verylsi]

Hi Anusha,

When you use generate you should always remember - it is not a run time function. Once synthesis is done for one generated condition , it will not change at run time, as it is hardware inside the FPGA and real electrical connections are made once you synthesize your design.

 

[FvM]

is there any way to do the instantiation inside always block

I presume you already know the answer is no.

It's nevertheless easy to connect the in-and outputs of the instantiated module with sequential code inside an always block by wires and regs.

 

[anusha vasanta]

Haa i know that we can't use instantiation inside an always block but heard that gen block can be written inside always block so i got the doubt of that kind.
Actually i had a tmp_reg contains one value and again i was assigning some other continous values to my tmp_reg like in the above mentioned code i know that it was wrong but i was unable to find a logic for that. help me thanku

 

[FvM]

but heard that gen block can be written inside always block so i got the doubt of that kind

It can't.

Actually i had a tmp_reg contains one value and again i was assigning some other continous values to my tmp_reg like in the above mentioned code i know that it was wrong but i was unable to find a logic for that.

At least to me ist completely unclear what you want to achieve here. Instead of posting code snippets that are illegal according to Verilog rules, you should describe what you exactly want to achieve.