Instantiation problem

[madalin1990]

hi !
I am writing a top entity containing two sub-entities:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TOP_dpimref_ROM is
      Port (
		mclk 	   : in std_logic;
      EppDB	   : inout std_logic_vector(7 downto 0);		-- port data bus
      EppAstb 	: in std_logic;								-- Address strobe
      EppDstb 	: in std_logic;								-- Data strobe
      EppWr 	: in std_logic;								-- Port write signal
      EppWait  : out std_logic		
		);
end TOP_dpimref_ROM;

architecture Behavioral of TOP_dpimref_ROM is


component dpimref is
    Port (
		mclk 	   : in std_logic;
      EppDB	   : inout std_logic_vector(7 downto 0);		-- port data bus
      EppAstb 	: in std_logic;								-- Address strobe
      EppDstb 	: in std_logic;								-- Data strobe
      EppWr 	: in std_logic;								-- Port write signal
      EppWait  : out std_logic;								-- Port wait signal
		data      : out std_logic_vector(7 downto 0);
		addr 	   : out std_logic_vector(3 downto 0);
		ROM_wr   : out std_logic
	);
end component;
	
component ram_sp_ar_aw is
    generic (
        DATA_WIDTH :integer := 8;
        ADDR_WIDTH :integer := 4
    );
    port (
        address :in    std_logic_vector (ADDR_WIDTH-1 downto 0);  -- address Input
        data    :inout std_logic_vector (DATA_WIDTH-1 downto 0);  -- data bi-directional
        we      :in    std_logic                                  -- Write Enable/Read Enable
 );
end component;

signal tmpWr : std_logic;
signal tmpData :std_logic_vector(7 downto 0);
signal tmpAddr :std_logic_vector(3 downto 0);
 

begin
Inst_dpimref : dpimref port map(
      mclk     =>  mclk,	    
      EppDB    =>  EppDB,	    
      EppAstb  =>	 EppAstb,
      EppDstb 	=>  EppDstb, 
      EppWr 	=>  EppWr,
      EppWait  =>  EppWait,
		data     =>  tmpData,
		addr 	   =>  tmpAddr,
		ROM_wr   =>  tmpWr
	);
	
Inst_ram_sp_ar_aw : ram_sp_ar_aw port map(
   	 address => tmpAddr, 
       data    => tmpData, 
       we      => tmpWr
);
end Behavioral;

I can't figure why I receive the following errors when running "Synthesize":

ERROR:Xst:2037 - Unit <TOP_dpimref_ROM>: Several tristates on signal tmpData<7> are sharing the same enable signal EppWr
ERROR:Xst:2037 - Unit <TOP_dpimref_ROM>: Several tristates on signal tmpData<6> are sharing the same enable signal EppWr
ERROR:Xst:2037 - Unit <TOP_dpimref_ROM>: Several tristates on signal tmpData<5> are sharing the same enable signal EppWr
ERROR:Xst:2037 - Unit <TOP_dpimref_ROM>: Several tristates on signal tmpData<4> are sharing the same enable signal EppWr
ERROR:Xst:2037 - Unit <TOP_dpimref_ROM>: Several tristates on signal tmpData<3> are sharing the same enable signal EppWr
ERROR:Xst:2037 - Unit <TOP_dpimref_ROM>: Several tristates on signal tmpData<2> are sharing the same enable signal EppWr
ERROR:Xst:2037 - Unit <TOP_dpimref_ROM>: Several tristates on signal tmpData<1> are sharing the same enable signal EppWr
ERROR:Xst:2037 - Unit <TOP_dpimref_ROM>: Several tristates on signal tmpData<0> are sharing the same enable signal EppWr
ERROR:Xst:415 - Synthesis failed

 

[ads_ee]

what are you doing in dpimref with the EppDB inout?

 

[madalin1990]

what are you doing in dpimref with the EppDB inout?

Well EppDB is used to write data in the internal address and data registers,and to indicate the adress of this registers.In this case is used as an input signal.

He is also used to send to the PC Adept Interface the values stored in those registers. Works as an output.

 

[ads_ee]

I suspect the error is caused by having the inout on both the top level port and the instantiated component. Therefore there are two drivers on the top level. The bi-directional signal should be implemented at the top level using only input and output ports of the dpimref block.

 

[madalin1990]

So dpimref should not have "data" as an inout , and I must think another implementation using an input "data" and an output "data".

 

[ads_ee]

Before running off and changing everything, you might want to see if one of the VHDL gurus around here has a better solution. I mostly use Verilog for my designs, but have used VHDL in the past.

 

[madalin1990]

I'm not a big fan of VHDL either. I use this language only because the Adept reference I use for my design is written in VHDL. once I'll have a good tested design, the first thing I'll do is "translate" it to Verilog.

Thank you for pointing the problem.
A good day,sir!

 

[FvM]

Generally the problem can't be siscussed without knowing how the said port signals are connected inside the components.

So dpimref should not have "data" as an inout

According to the component definition data of dpimref is a pure output port, connected erroneously to an inout port of ram_sp_ar_aw.

 

[ads_ee]

Well I was certainly looking at the wrong signal (EppDB). Don't know why I was looking at that one :-?

Yup the inout on the ram_sp_ar_aw isn't going to work. You can't have internal tri-states in an FPGA.

 

[FvM]

You can have internal tristates with most synthesis tools, but they are translated to muxes. HDL designers might consider them useful in some cases though.

Connecting an output to an inout port, as in the present example is only possible, if the the inout tristate is never enabled.

 

[ads_ee]

Yeah most tools will convert, but I'd rather the tool spent every clock cycle translating the rest of my logic than spend time converting tri-states to muxes. This is especially true when I can easily write those muxes myself in the first place. No sense in increasing my run time any more than I have too.

 

[madalin1990]

I have corrected some of the mistakes in my initial code. I was not carefull and forget to declare the dpimref "data" signal as an inout.
I now understand why add_ee was considering EppDB being a wrong signal.Without "data" as an inout, EppDB would work only as an input signal.
So now my top design has 2 blocks:

component dpimref is
     Port (
		mclk 	   : in std_logic;
      EppDB	   : inout std_logic_vector(7 downto 0);		-- port data bus
      EppAstb 	: in std_logic;								-- Address strobe
      EppDstb 	: in std_logic;								-- Data strobe
      EppWr 	: in std_logic;								-- Port write signal
      EppWait  : out std_logic;								-- Port wait signal
	   data     : inout std_logic_vector(7 downto 0);
		address 	   : out std_logic_vector(3 downto 0);
		Swrite : out std_logic
	);
end component;

AND

component ram_sp_ar_aw is
     generic (
        DATA_WIDTH :integer := 8;
        ADDR_WIDTH :integer := 4
    );
    port (
        address :in    std_logic_vector (ADDR_WIDTH-1 downto 0);  -- address Input
        data_mem    :inout std_logic_vector (DATA_WIDTH-1 downto 0);  -- data bi-directional
        we      :in    std_logic                                 -- Write Enable/Read Enable
    );
end component;

I must connect the inout "data" of dpimref to inout "data_mem" of the ram_sp_ar_aw.
I tried declaring some internal registers hopping to realise this :

signal dpimref_reg :std_logic_vector(7 downto 0);
signal mem_reg :std_logic_vector(7 downto 0);

data <= mem_reg when ( tmpWr = '0') else (others=>'Z');
data_mem <= dpimref_reg when ( tmpWr = '0') else (others=>'Z');

But it was a longshot ,because VHDL didn't recognised this as I would hoped,resulting in an error.
So any idea on how should i connect this two inout ports?

 

[TrickyDicky]

just declare a signal data in the top level, and connect it to both the data_mem of the ram_sp_ar_aw entity and data port of the dpimref signal.

But the problem you have is that you have 2 blocks accessing the same inout bus, and there are no internal tri-states. You should have separate in and out signals for each component, and have something else at the top level that decodes the single inout port into separate in and out busses for the separate components.

 

[madalin1990]

I got the idea.Let's see how this works.