vlsiengg.
Newbie level 1
i want to replace each adder in module pt4 with adder named sara..i had done it with output y0=(x0+x1+x2+x3)<<6..but showing error..please help
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 module pt4( input wire [7:0]X0,X1,X2,X3, output reg [14:0]Y0, output reg [14:0]Y1, output reg [14:0]Y2, output reg [14:0]Y3); always@(*) begin sara f1(X0,X3,h1); sara f2(h1,X1,h2); sara f3(h2,X2,h3); Y0= h3<<6; Y1=(X0+X3+((~X1)+8'd1)+((~X2+8'd1)))<<6; Y2=((X1+((~X2)+8'd1))<<5)+((X0+((~X3)+8'd1))<<6)+((X0+((~X3)+8'd1))<<4); Y3=((X1+((~X2)+8'd1))<<6)+((X1+((~X2)+8'd1))<<4)+((X3+((~X0)+8'd1))<<5); end endmodule
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 module sara( input [7:0] a, input [7:0] b, input cin,m, output [7:0] s, output cout ); wire g0,g1,g2,g3,g4,g5,g6,g7,c0,c1,c2,c3,c4,c5,c6,c7, co1,co2,co3,co4,co5,co6,co7; add u1(a[0],b[0],cin,g0,c0,s[0]); mux v1(g0,c0,m,co1); add u2(a[1],b[1],co1,g1,c1,s[1]); mux v2(g1,c1,m,co2); add u3(a[2],b[2],co2,g2,c2,s[2]); mux v3(g2,c2,m,co3); add u4(a[3],b[3],co3,g3,c3,s[3]); mux v4(g3,c3,m,co4); add u5(a[4],b[4],co4,g4,c4,s[4]); mux v5(g4,c4,m,co5); add u6(a[5],b[5],co5,g5,c5,s[5]); mux v6(g5,c5,m,co6); add u7(a[6],b[6],co6,g6,c6,s[6]); mux v7(g6,c6,m,co7); add u8(a[7],b[7],co7,g7,c7,s[7]); mux v8(g7,c7,m,cout); endmodule
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 module add( input a,b,cin, output g,c,s ); wire p0,w0; xor(p0,a,b); and(g,a,b); xor(s,p0,cin); and(w0,p0,cin); or(c,g,w0); endmodule
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 module mux( input a,b,m, output z ); wire r0,r1; and(r0,~m,a); and(r1,m,b); or(z,r0,r1); endmodule