buenos
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actel, EDN, inout ports
hu
can we instantiate an EDN into an actel (free Libero) VHDL project and synthesise it? (it would be a result of another project, which is a core written in verilog)
can we synthesize an EDN file from verilog (with actel-synplify or with anything else in general) with inout ports on it? (with "disable IO insertion option") or I have to route in/out/oe signals separately?
hu
can we instantiate an EDN into an actel (free Libero) VHDL project and synthesise it? (it would be a result of another project, which is a core written in verilog)
can we synthesize an EDN file from verilog (with actel-synplify or with anything else in general) with inout ports on it? (with "disable IO insertion option") or I have to route in/out/oe signals separately?