cganeshprabhu
Junior Member level 3
Hi,
how to instantiate a vhdl dut in verilog testbench ?
If it is a verilog testbench for verilog dut then it is like .....
eg:
dff dff1(list of signals)
.
Please suggest me how to do for a vhdl dut.
Regards,
Ganesh
how to instantiate a vhdl dut in verilog testbench ?
If it is a verilog testbench for verilog dut then it is like .....
eg:
dff dff1(list of signals)
.
Please suggest me how to do for a vhdl dut.
Regards,
Ganesh