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instantiating a vhdl dut in verilog testbench

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cganeshprabhu

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Hi,

how to instantiate a vhdl dut in verilog testbench ?

If it is a verilog testbench for verilog dut then it is like .....
eg:

dff dff1(list of signals)
.

Please suggest me how to do for a vhdl dut.

Regards,
Ganesh
 

Thomson

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There are mainly two methods to realize this function:
(1) use the tools which can conduct the mix-hdl simulation such as Modelsim and so on
(2) For VCS that is unable to implement this function, then you should follow the process below:
a. create a directory named worklib
b. under this dirctory use the vhdlan commands to map the vhdl source file into the dirctory-- vhdlan -work worklib m1.vhd
c. in the environment, instantiate the vhdl module as m1 m1_ins();
d. in the VCS options: -mhdl \
+ vhdllib+worklib.m1
 

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