"Instantiated result is giving dont care values"

[aruna siddappa]

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
module mult_3 (
    input wire [3:0] x,
    input wire en,
    output reg [11:0] y);
      always @ (*) begin
          if(en) y=(x*3); else y=0;
    end 
      endmodule
 
module mult_9 (
    input wire [3:0] x,
    input wire en,
    output reg [11:0] y);
       always @ (*) begin
        if(en) y=(x*9); else y=0;
            end
 
endmodule
 
module mult_11 (
    input wire [3:0] x,
    input wire en,
    output reg [11:0] y);
always @ (*) begin
        if(en) y=(x*11); else y=0;
    end 
     
endmodule
 
module mult_83 (
    input wire [3:0] x,
    input wire en,
    output reg [11:0] y);
 
        always @ (*) begin
        if(en) y=(x*83); else y=0;
    end 
 
endmodule
 
module top (
    input wire [3:0] in,
    input wire [1:0] data_id,
    output [11:0] result);
        wire en1,en2,en3,en4;
 
assign en1=(~data_id[1] & ~data_id[0]);
assign en2=(~data_id[1] & data_id[0]);
assign en3=(data_id[1] & ~data_id[0]);
assign en4=(data_id[1] & data_id[0]);
 
 
        mult_3 dut1     (.x(in),.en(en1),.y(result));
        mult_9 dut2     (.x(in),.en(en2),.y(result));
        mult_11 dut3    (.x(in),.en(en3),.y(result));
        mult_83 dut4     (.x(in),.en(en4),.y(result));
endmodule

---

The result is initially 0, then in the place of 1 it's showing x

 

[danadakk]

When you post use the code tags to maintain formatting so its more readable.

Regards, Dana.

 

[barry]

I’m not a verilog guy, so i could be wrong, but it looks to me like you’ve got four sources driving “result”.

 

[aruna siddappa]

Yes, there are 4 sources driving the result.
dut1,2,3,4 are 4 instances which are driving result.
If i give only one instance commenting other three i get correct result. Please help me what is wrong in the code
mult_3 dut1 (.x(in),.en(en1),.y(result)); // mul by 3
/* mult_9 dut2 (.x(in),.en(en2),.y(result)); // mul by 9
mult_11 dut3 (.x(in),.en(en3),.y(result)); // mul by 11
mult_83 dut4 (.x(in),.en(en4),.y(result));*/ //mul by 83

 

[dick_freebird]

"X" is not "don't care", it's "don't know". Look to initializations of latch, 'flop, memory elements.

 

[KlausST]

Hi,

I´m not sure ... but can it be a setup and/or hold timing violation that cuases the "X"?

Klaus

 

[dick_freebird]

That is one way, but then the "X" would appear following
a clock / latch edge, from a previously unkown datum (or,
clock / latch state itself, being unknown).

 

[barry]

Yes, there are 4 sources driving the result.
dut1,2,3,4 are 4 instances which are driving result.
If i give only one instance commenting other three i get correct result. Please help me what is wrong in the code
mult_3 dut1 (.x(in),.en(en1),.y(result)); // mul by 3
/* mult_9 dut2 (.x(in),.en(en2),.y(result)); // mul by 9
mult_11 dut3 (.x(in),.en(en3),.y(result)); // mul by 11
mult_83 dut4 (.x(in),.en(en4),.y(result));*/ //mul by 83

Again, I'm not a verilog guy, but I AM a VHDL guy and a hardware guy, and in neither of those domains are you allowed to tie multiple outputs together. Maybe Verilog lets you do this (yet another reason to prefer VHDL), but it's just wrong.

Just think: One output is high and the other output is low, what happens?

 

[aruna siddappa]

I got the fix, i used 4 wires to copy the result and then used process to store the result back.

module top (
    input wire [3:0] in,
    input wire [1:0] data_id,
    output reg [11:0] result);
        wire en1,en2,en3,en4;
        wire [11:0] res3;
        wire [11:0] res9;
        wire [11:0] res11;
        wire [11:0] res83;
   
    assign en1=(~data_id[1] & ~data_id[0]);
    assign en2=(~data_id[1] & data_id[0]);
    assign en3=(data_id[1] & ~data_id[0]);
    assign en4=(data_id[1] & data_id[0]);

    mult_3 dut1     (.x(in),.en(en1),.y(res3));    // mul by 3
    mult_9 dut2     (.x(in),.en(en2),.y(res9));     // mul by 9
    mult_11 dut3    (.x(in),.en(en3),.y(res11));      // mul by 11
    mult_83 dut4     (.x(in),.en(en4),.y(res83));     //mul by 83
   
    always @ (*) begin
    case(data_id)
        2'b00: result=res3;
        2'b01: result=res9;
        2'b10: result=res11;
        2'b11: result=res83;
        default:result=0;
    endcase
end
endmodule

Thanks everyone