instaniatinga a module at every clock edge

[pratikjain]

i have to call a module several times at every clock edge....since we cannot instantiate a module in an always block i need some other way to do so...pls help

 

[mrflibble]

Are we talking about something that will synthesise to actual hardware? If yes, could you post the module that you are talking about?

 

[TrickyDicky]

You cannot dynamically instatiate anything. That would be like asking a CPU to create another CPU when it got too busy.

 

[pratikjain]

yes,i need to synthesize my code also.im posting the module and i want to call this module 256 times for different values of in1,in2,in3,in4.

module invisible(in1,in2,in3,in4,wmk,final_out,clk,rst);
input[7:0] in1,in2,in3,in4;
input clk,rst;
input[1:0]wmk;
output[7:0] final_out;
wire[7:0] neighbour_out,multipler_out1,multiplier_out2;
neighbour n1(neighbour_out,clk,rst,in2,in3,in4);
multipliermux m1(multiplier_out1,multiplier_out2,clk,rst,in1,neighbour_out,wmk);
adder a1(final_out,clk,rst,multipler_out1,multiplier_out2);
endmodule

 

[Scrts]

You can't instantiate a module dynamically. Think of the hardware, not the software. You can instantiate the same module as many times as Your FPGA fits. So use the same module and change input parameters or instantiate the same module more than one time assigning different signals.

 

[mrflibble]

The concept of "call a module multiple times" doesn't make too much sense when using it in the context of synthesized hardware.

You can however instantiate a module multiple times, for example using the generate/endgenerate verilog construct.

hope that helps

 

[childs]

if u need this module to process the 256 signals/data in1, in2, in3.... till in256. One way of doing so is by having 256 such modules to serve each signal/data.