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INSICIVE14.1 cannot generate delay on assignment

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littlebu

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I am running OVM env together with some behavior model descripted in verilog.
But seems it is never working....

assign #0.2ns A = B;

But below is OK (changed to always)

always @ * A <= #0.2ns B;

Since another env without OVM is OK, so i doubt it is related with OVM or some delay mode setting.
 

littlebu

Member level 1
Joined
May 19, 2007
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33
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4
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0
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1,286
Activity points
1,449
I am running OVM env together with some behavior model descripted in verilog.
But seems it is never working....

assign #0.2ns A = B;

But below is OK (changed to always)

always @ * A <= #0.2ns B;

Since another env without OVM is OK, so i doubt it is related with OVM or some delay mode setting.

i have found root cause is SEQ_UDP_DELAY option, simulation is OK after removing this option.!!
 

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