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Inputs on my first PCB for AC motor driver.

ghoetic

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I am making my first ever real PCB for my second AC motor driver and and i would like some input on the design.
I relied on microchip AN1660 as guide.
 

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KlausST

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Hi,

I'm just working on an old tablet ... thus I can't open the .zip file.

What about uploading a picture or pdf?

Klaus
 

KlausST

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Hi,

I'd say it's no suitable SMPS design.
It may work or not.
I doubt it can work reliably.
I doubt it can fulfill EMI/EMC requirements.
I doubt it fulfills all the creepage distance and clearance requirements.

I recommend to
* read through the datasheets, especially the chapters "PCB layout considerations" and "design considerations"
* read through application notes, that every semiconductor manufacturer provides.... for free
* go through reference desings
* read through threads here in the forum

I wonder why you used no GND plane. (No, a copper pour is no GND plane). There is plenty of free board space. And it takes less than just a couple of minutes to draw a GND polygon (without other traces, without cuts)...and add some vias.

Klaus
 

ghoetic

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Hi,

I'd say it's no suitable SMPS design.
It may work or not.
I doubt it can work reliably.
I doubt it can fulfill EMI/EMC requirements.
I doubt it fulfills all the creepage distance and clearance requirements.

I recommend to
* read through the datasheets, especially the chapters "PCB layout considerations" and "design considerations"
* read through application notes, that every semiconductor manufacturer provides.... for free
* go through reference desings
* read through threads here in the forum

I wonder why you used no GND plane. (No, a copper pour is no GND plane). There is plenty of free board space. And it takes less than just a couple of minutes to draw a GND polygon (without other traces, without cuts)...and add some vias.

Klaus
Thanks for the input. i will surley check more ref designs.

could you elaborate on a ground plane? i made the top layer gnd for the non isolated and isolated side.
 

KlausST

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Hi,

could you elaborate on a ground plane? i made the top layer gnd for the non isolated and isolated side.
Read through some threads here.
I already had replied with lenghty explanations several times.
I'm sure you will find them with a forum search..

Again: you used copper pour ... it is cut in pieces

Maybe this helps:
Imagine an area of 5m x 5m of thick plastic foam on a lake. It's easy to walk on it.
Now cut the foam area in pieces of random size .... and try to walk on it.

Klaus
 

ghoetic

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Hi,


Read through some threads here.
I already had replied with lenghty explanations several times.
I'm sure you will find them with a forum search..

Again: you used copper pour ... it is cut in pieces

Maybe this helps:
Imagine an area of 5m x 5m of thick plastic foam on a lake. It's easy to walk on it.
Now cut the foam area in pieces of random size .... and try to walk on it.

Klaus
Thanks for your time!
Okay i am starting to understand. will get up to par, and report back with an updated design.
 

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Some additional remarks.

1. KlausST commented already about the fragmented copper pour. I notice that you have placed jumper traces to connect the HV ground isles. Why not almost flooding the bottom side and placing many redundant bridge vias? Although the created ground can't compete with a true ground plane on a multilayer board, it may suffice for this design.

2. I see insufficient clearance and creepage in many places, e.g. 0.4 mm between HV DC and PE at the heat sink mount, also < 2 mm between HV and isolated 5V below the 5V DC/DC.

3. I expect problems in the "wide spread" gate driver traces. Low side gate nets and return have huge return loop.

4. You have zero DC bus bypass capacitors except for the bulk electrolyte capacitors, separated by a probably inductive current shunt.

- - - Updated - - -

Even worse is the 0.25 mm clearance between DC- and high side source and gate nets around the gate driver IC for 325V working voltage.

Does EasyEDA support net classes with different clearance rules or better class-to-class rules? Without it, it's rather difficult to design a mixed controller and HV power PCB.
 

ghoetic

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Some additional remarks.

1. KlausST commented already about the fragmented copper pour. I notice that you have placed jumper traces to connect the HV ground isles. Why not almost flooding the bottom side and placing many redundant bridge vias? Although the created ground can't compete with a true ground plane on a multilayer board, it may suffice for this design.

2. I see insufficient clearance and creepage in many places, e.g. 0.4 mm between HV DC and PE at the heat sink mount, also < 2 mm between HV and isolated 5V below the 5V DC/DC.

3. I expect problems in the "wide spread" gate driver traces. Low side gate nets and return have huge return loop.

4. You have zero DC bus bypass capacitors except for the bulk electrolyte capacitors, separated by a probably inductive current shunt.
Thousand thanks!

1. Currently working on two identical planes for bot and top, but with just vias for the gnd. :thumbsup:

2. i set the clerance to 0.4mm concidering the to220 package limitation. this could be changed to a to247 to overcome this. but i wanted to do this design now that i have already bougth the igbts. but going to make bigger keepout area for the heatsink connection.

3. tips to minimize the gate drive traces?

4. get 1uf film capacitor near the bus?
 

ghoetic

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New design, 1mm clearance, slimmer board, slots between TO220 legs. ground planes, thighter gate drive, the best i can do without trying to put the IC under the bridge, film cap.

6oE2LMq.png

KV0JgeA.png

https://imgur.com/a/26PSZTg

Gladly appricate some new input!

Thanks!
 

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KlausST

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Hi,

Much better now.

I didn't check clearance and creepage distances.


The red GND areas are useless, at least the very very most of them.
Keep them, if you like them.

But reduce the traces in the blue layer.
I miss thermals at the smd pads.

It's hard to detect details. Maybe increase picture resolution next time.
Use a lossless picture format like .png.

Currently I'm working on my tablet. In half a day I'm on my PC and could show some improvements.

Klaus
 

ghoetic

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Hi,

Much better now.

I didn't check clearance and creepage distances.


The red GND areas are useless, at least the very very most of them.
Keep them, if you like them.

But reduce the traces in the blue layer.
I miss thermals at the smd pads.

It's hard to detect details. Maybe increase picture resolution next time.
Use a lossless picture format like .png.

Currently I'm working on my tablet. In half a day I'm on my PC and could show some improvements.

Klaus
Thanks yet again for your valuable input!

regarding creepage and clerance, i just need functional i guess, because the interface is isolated. but any reference? i made a quick stop by the smps.us to read about it.
do you mean thermal vias?

Generally should i use pads (via with exposed copper) or just vias any pros cons?

going to work on your suggestions!
 

KlausST

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Hi,

regarding creepage and clerance, i just need functional i guess, because the interface is isolated.
No! Functional isolation is just within one voltage net.

Especially where you have galvanically isolated parts you need at least "basic isolation".
It depends on a lot of things. Your countrie´s regulations, voltages, dirt, altitude, protection level....
You urgently need through some (boring and often hard to understand) regulations.

There are more or less reliable documents in the internet and even video tutorials.

****
Example:
Even if an optocoupler is rated for 4000V/1min it does not mean that it is legal to use it on an 230V AC application.
For many 230V AC applications you should go for 7mm (at least 6mm) of creepage distance.
Many optocouplers can not satisfy this.

Maybe your optocouper is suitable, I´m not sure.... but your DCDC converter most probaly is not according safety regulations.
Again: it depends on a lot of parameters.

AND:
hard corners (at areas) are a NO GO. They increase electric field strength and thus functionallly reduce creepage distance.
You need to use arcs.

do you mean thermal vias?
No. Thermals on the SMD pads that are connected to the copper pour. I can´t recognize them.


*****
Layout:
Put Q7 close to the relay, thus you shorten the traces that carry the relay current. And you don´t need that wide trace.
Feed the control trace on the red layer as much as possible. Maybe use several short pieces. Don´t cut the GND plane on the blue layer.
(My recommendation: from pad to the inner of the IC, then in direction of U5 as much as possible.)

Maybe R24 goes to an ADC. Then put R24 (not R23...) close to the ADC. This increases the precision because it better relates to ADC_GND. Consider to use a capacitor in parallel to R24.
Feed the trace from R23 to R24 on the red layer as much as possible. Maybe use several short pieces. Don´t cut the GND plane on the blue layer.

R12, R22, R23 ... I think they need more clearance around...

The supply trace to R25/LED3 could be easily shortened on the blue layer ... by moving the via in direction of pin10 of U1.

Be sure R26 is a low impedance one. No wirewound.

The traces to the power transistors are rather narraw. I don´t know your schematic ... but usually they carry fast high peak current signals... and they need a suitable feedback path.
Mind: There is no signal "from A to B" always has to be the feedback path from B to A. And it needs to be routed as carefully as the way from A to B. Best if it runs exacly the way from A to B on the opposite layer. Otherwise you get high series inductance causing ringing (worst case: self destructive), high EMI and maybe low efficiency.

There may be more issues.

Klaus
 

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Hi,


No! Functional isolation is just within one voltage net.

Especially where you have galvanically isolated parts you need at least "basic isolation".
It depends on a lot of things. Your countrie´s regulations, voltages, dirt, altitude, protection level....
You urgently need through some (boring and often hard to understand) regulations.

There are more or less reliable documents in the internet and even video tutorials.

****
Example:
Even if an optocoupler is rated for 4000V/1min it does not mean that it is legal to use it on an 230V AC application.
For many 230V AC applications you should go for 7mm (at least 6mm) of creepage distance.
Many optocouplers can not satisfy this.

Maybe your optocouper is suitable, I´m not sure.... but your DCDC converter most probaly is not according safety regulations.
Again: it depends on a lot of parameters.

AND:
hard corners (at areas) are a NO GO. They increase electric field strength and thus functionallly reduce creepage distance.
You need to use arcs.


No. Thermals on the SMD pads that are connected to the copper pour. I can´t recognize them.


*****
Layout:
Put Q7 close to the relay, thus you shorten the traces that carry the relay current. And you don´t need that wide trace.
Feed the control trace on the red layer as much as possible. Maybe use several short pieces. Don´t cut the GND plane on the blue layer.
(My recommendation: from pad to the inner of the IC, then in direction of U5 as much as possible.)

Maybe R24 goes to an ADC. Then put R24 (not R23...) close to the ADC. This increases the precision because it better relates to ADC_GND. Consider to use a capacitor in parallel to R24.
Feed the trace from R23 to R24 on the red layer as much as possible. Maybe use several short pieces. Don´t cut the GND plane on the blue layer.

R12, R22, R23 ... I think they need more clearance around...

The supply trace to R25/LED3 could be easily shortened on the blue layer ... by moving the via in direction of pin10 of U1.

Be sure R26 is a low impedance one. No wirewound.

The traces to the power transistors are rather narraw. I don´t know your schematic ... but usually they carry fast high peak current signals... and they need a suitable feedback path.
Mind: There is no signal "from A to B" always has to be the feedback path from B to A. And it needs to be routed as carefully as the way from A to B. Best if it runs exacly the way from A to B on the opposite layer. Otherwise you get high series inductance causing ringing (worst case: self destructive), high EMI and maybe low efficiency.

There may be more issues.

Klaus
I have listen to your points and improved the design again thanks!

done most of your suggestions.

replaced the inductive wirewound with two non inductive power resistors in pararell to meet the power and ohm requirement.
bent the TO-220 legs,
slots under the DC/DC and OPTO.
increased PE coverage.

2oz copper.

Getting ready to order the PCB, this will not be a product, just one off for education/hobby.

The traces from the gate resistors i thickened from 0.5mm to 1mm.
Cant seem to get much thicker before the gate resistor, opinion?

Vias. should i add more? i exposed copper so i can use some of em as testpoints.

https://ibb.co/gZPB1mc
https://ibb.co/B2L0LsC
https://ibb.co/1nLvwTC

can add gerber if you want.
 

KlausST

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Hi,

The traces from the gate resistors i thickened from 0.5mm to 1mm.
Cant seem to get much thicker before the gate resistor, opinion?
No need to get even wider.
on the first pictures they rather looked like 0.15mm than 0.5mm.
The resistance with 1mm is not the problem now. Now it´s the inductance causing high impedance... you now can´t lower the impedance (significantly) by increasing the width or thickness. Even 10mm won´t be much of a benefit.
It now more depends on the missing return path.

Vias. should i add more? i exposed copper so i can use some of em as testpoints.
You ask.. So I repeat my opinion: The top GND is useless. You might add vias as you like, but it won´t be any significant electrical improvement.


If there will be a spark from230V area to isolated area, then I predict it will be close to C16 because of the sharp edge opposite to 16.


Mind to use standoffs at the heatsink. Solderstop is no isolation according safety regulations.


I assume it will work.
But the same time I assume it is not according safety regulations and EMI/EMC regulations.


Use a fire proof mat. Not that I think it will immediately cause fire, but in case there is some little conductive dirt..and it causes a spark ... there is a good chance that it won´t slef extinguish because of low functional isolation.
This is especially true for the 325V DC bus.


Use it on your own risk, don´t let anybody else touch it. Nothing.


Let us know how it behaves...

Klaus
 

ghoetic

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Hi,


No need to get even wider.
on the first pictures they rather looked like 0.15mm than 0.5mm.
The resistance with 1mm is not the problem now. Now it´s the inductance causing high impedance... you now can´t lower the impedance (significantly) by increasing the width or thickness. Even 10mm won´t be much of a benefit.
It now more depends on the missing return path.


You ask.. So I repeat my opinion: The top GND is useless. You might add vias as you like, but it won´t be any significant electrical improvement.


If there will be a spark from230V area to isolated area, then I predict it will be close to C16 because of the sharp edge opposite to 16.


Mind to use standoffs at the heatsink. Solderstop is no isolation according safety regulations.


I assume it will work.
But the same time I assume it is not according safety regulations and EMI/EMC regulations.


Use a fire proof mat. Not that I think it will immediately cause fire, but in case there is some little conductive dirt..and it causes a spark ... there is a good chance that it won´t slef extinguish because of low functional isolation.
This is especially true for the 325V DC bus.


Use it on your own risk, don´t let anybody else touch it. Nothing.


Let us know how it behaves...

Klaus
Yet again thank you, i will round all the corners.
why im confused about top gnd and vias is two fold, one is caught someone saying use many as many vias as you want in your design, more is better to a degree.
if its not too much to ask take a look at AN1660 from microchip. uploaded gerbers to a viewer and looked at the layers and based alot on the design on that.
Im sorry if i quite dont understand, but could you link something about heatsink standoffs?

I hope im not bothering you, im really trying to learn and do my best and im super grateful for your advice!
 

KlausST

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Hi,

why im confused about top gnd and vias is two fold, one is caught someone saying use many as many vias as you want in your design, more is better to a degree.
I'm saying useless, because 99% of the area is free of current. And I think it's good the way it is.
One good GND plane is better than two mediocre planes.

If you have one solid area of concrete .... it's not much of an improvement when you put smaller pieces of concrete on top of them.

Klaus

- - - Updated - - -

Added...

Im sorry if i quite dont understand, but could you link something about heatsink standoffs?
Heatsinks are made from conductive metal. You connected them to Earth ground. So you need to electrically isolate them from top layer signals. Plastic standoffs maybe could help.

Klaus
 

schmitt trigger

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Hi,
Again: you used copper pour ... it is cut in pieces

Maybe this helps:
Imagine an area of 5m x 5m of thick plastic foam on a lake. It's easy to walk on it.
Now cut the foam area in pieces of random size .... and try to walk on it.

Klaus
Excellent analogy.
 

KlausST

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Hi,

AN1660 of Microchip.

To say the least: I´m shocked.
Here a view of the AN1660 Gerber files:
AN1660.jpg
Left side they say "isolated", right side is hot 230V AC mains side.

In the Application note they say "safe to touch".
Maybe this is "functional isolation" (I doubt even this) but functionally isolated parts are not "safe to touch".

***
I mean... There are application notes that show the function of a circuit. This is O.K. And in best case there is some remark that it not designed in the meaning of safety.
But application notes often are used by not that experienced developers... as reference design.
And here the sentence "is safe to touch" is what shocks. It lulls oneself into a false sense of security.

I know the regulations for safety are different in each country, they are hard to read and hard to understand...and often expensive.

Goethic: Currently I see your design more safe than the AN, but still not according regulations.
Please try to find a person in your country who can help you with this.

Klaus
 

FvM

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I know the regulations for safety are different in each country, they are hard to read and hard to understand...and often expensive.
Don't agree. IEC 61010 and similar standards for specific application ranges are in force almost worldwide. Mains voltage <300 V, overvoltage category II, pollution degree 2 requires 1.5 mm PCB clearance and creepage for basic insulation, doubled value for reinforced insulation.

Reinforced insulation is required between mains circuit and control circuits that can be touched directly or indirectly.

Basic insulation must be achieved between mains circuit and PE, if PE has sufficient current capacity.

- - - Updated - - -

I agree with your safety assessment of the AN1660 board. Isolation is flawed by connecting one transformer secondary winding to the mains side and the other to the "isolated" low voltage side. The board layout is just continuing the fault.
 

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