Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Input voltage drops into UVLO with transient load

Not open for further replies.


Full Member level 3
Nov 8, 2014
Reaction score
Trophy points
Activity points
Hi Guys,

This is probably a long shot as I know the information I can give is very limited, so realistically I am not expecting a definitive answer by any means (this is not my design, hence why the information is limited). I have forward power supply that has multiple outputs coming from the transformer, I have no specifications as you would expect just the required input voltage and the output voltages with rough current capabilities. The situation is that the supply work fine with a transient load on one of the outputs, however when the input voltage is dropped to a certain voltage below the specified input voltage the input supply drops 20V to the uvlo of the controller. It then gets stuck in the start up sequence where it trys to start up but cannot. I was wondering if anyone had this experience where the input voltage level drops like this (the current isn't restricted from the input supply btw), in my experience I have never seen an input voltage been dragged down to UVLO like this, any ideas?

Perhaps source impedance is too high (eg PV)
Thus startup drop is big near UVLO conditions.

The UVLO is designed to prevent switching current from increasing beyond the maximum rated limit, hence, preventing the device from overheating.

If this does not fit your application, then your VI characteristics need to be analyzed.

I was thinking it might have something to do with the impedance because the voltage is being sent down a cable. When the length is increased the voltage drop is higher (i.e input voltage is lower) the thing that confused me was that the power supply runs fine until the load is stepped up which made me think its something to do with the VI limitations of the design. Are there ways to compensate for a higher impedance input?

This may be telling you that a designed "hiccup" mode
capable of overcoming UVLO is needed.

If the load is truly transient or the source inductive (or
inductive-acting) then perhaps a larger input filter can
be your "bridge to emotional safety". Give some thought
to the nature of the source supply.

Now UVLO's primary purpose is to ensure that the power
devices can be well drivem. Old school power MOSFETs
needed 8-10V so you see many old school PWMs with
8V-range UVLO. Inappropriate for a "logic level MOSFET"
or a BJT based switcher, although in many of these PWMs
there is analog functionality which woulf fail not that much
lower (because they expected 8V cliff and had no need to
try and make the 5V reference work well below, say, 7V).

If you have a saggy source, perhaps you want a secondary
loop or even a secondary converter, crude but low voltage
functional, which can pump power at conditions below
where your high quality, normal input range converter is
A sudden transient load, provided it is very short, may be overcome by fitting some large energy storage capacitors across either the dc input to the supply, or across the particular dc output that is being loaded.

Which is more preferable will depend on the relative dc voltages involved.
Stored energy is proportional to voltage squared, so for any given total capacitance, the energy storage capacity will work much more effectively if carried out at a higher voltage.

As you mention the input voltage drops by 20v, I am assuming the normal input dc voltage is quite high, so that may be the best place to fit some suitably sized electrolytics.

An alternative strategy might be some ultra capacitors at the dc output.
Either solution is worth looking into, particularly the relative costs.

I would analyze the transient load ESR ( MOSFET + coil ) and compare that with the source ESR. If the voltage divider relationship for this transient explains your drop then by determining the pulse duration you can use a super low ESR cap to provide the RsC duration x3 or more and choose C. with the ESRc << ESRload (<10%)

naturally placing this low ESR Cap close to the load shunts the ESR of cable and source.

These things can happen with an unsuitable combination of UVLO, source impedance, soft start and short circuit respectively overload protection. In so far it's an everyday problem in power supply design.

We would need more information about the design for specific help.

Not open for further replies.

Part and Inventory Search

Welcome to