Input on New Spartan 3 Web Pack Design

[DPE]

I've begun a crash course on FPGA design having not touched them since school more than a decade ago. I've been tasked with designing an FPGA-based solution for the following:

Digitize 4096 samples of 16 channels of 1kHz audio in parallel, perform FFT's on each, and calculate various SNR/THD/IP3 characteristics.

We'll be using Xilinx and would like to get by with the Web Pack version of ISE. I've currently zero'ed in on the xc3sd1800a. This FPGA will not have enough memory to store all of the data; so I'm planning on adding some external memory.

My current algorithm is as follows:
1. Have the FPGA monitor a set of three pins which will be used to kickoff the FPGA to read in the serial data from the digitizers (sampled at 192kHz).
2. As each 24-bit result is received, have the FPGA turn around and push the 16 24-bit words to the external RAM. Repeat this process 4096 times.
3. Have the FPGA read in the 16 data sets from external memory serially and perform the FFT and other calcuations.
4. Make the results available to the host processor (perhaps JTAG register reads by the host).

Having never done this before, I'm looking for any advice from experts. Does this plan sound reasonable? How overly ambitious is this for my first project? Any pitfalls you can see coming in either the HW or SW design that could be avoided with bit of wisdom from an experienced designer? Any particular books that you would recommend? I just purchased Chu's book on the Spartan 3. I plan on lifting what I can from the eval board schematic for hardware design.

Sorry for the long-winded explanation with no particular technical question. But I would really appreciate anyone's feedback!

 

[farhada]

This is a pretty big project and you definitely need some IPs for the TFT and noise calculation or else you will spend a lot of time designing those.

The steps you mentioned sound OK but needs many more steps in between before you are done.

You can choose to do everything in parallell which will take a lot of resources on t he FPGA or design in pipeline which means more complicated data flow but smaller area.

If you do not need to do this in real time, I would suggest you go for Altera based FPGA, use the Freely available Nios processor and perform the TFT and noise calculation in SW, this way the complexity of your design will be minimum when it comes to actual FPGA design. But if you insist on using Xilinx, then you have steep time consuming road ahead of you.

Just my 2c,

Best regards,
Farhad Abdolian

 

[Rob B]

It has been a while since I used ISE but I think the WebPack may be too limited to synthesize a design of that complexity.

Are you planning on using a MicroBlaze or other 'soft' CPU to manage operations in the system?

 

[DPE]

I wasn't planning on it, but that's why I'm here looking for advice. My plan was to use an SRAM controller and FFT engine provided in the ISE environment, and then write some VHDL/Verilog to handle the data acquistion which will just be 4096 x 16 executions of code to grab a 24-bit serial number and then write it to external memory. And then something similar for the data crunching.

In my mind I picture toggling a pin to start a state machine in the FPGA:
1. On toggle, begin data acquisition.
2 After 4096 conversion are stored, loop through the FFT routine
a. Perform 4096 external memory reads, placing the data in FFT input space.
b. Perform FFT.
c. Perform SNR calculation.
d. Store result.
e. Loop back to 2a and repeat 15 more times.
3. Toggle a pin to indicate that the routine is complete
4. Move data to host.

Does this sound too complicated to do in strictly VHDL/Verilog? Would it make sense make use of the availble CPU functionality?

 

[farhada]

Sure you can do this without any problem if you have the FFT IP and it fits inside your FPGA.
But make sure you have a good simulation environment, debugging a FFT algorithm in VHDL will take a long time in simulation.

How much time do you have to do this project?

 

[DPE]

The hardware design is due in two days. After that I have 6 weeks of development time with a Xilinx eval board and an eval board for the ADC. The two eval boards should be very representative of the final HW design with respect to the aspects that I'm interested in (the ADC, the FPGA, and the external memory).

 

[farhada]

Interesting, thanks for the update, I would really appreciate it if you keep us informed about your progress. I am curious about your final report to see how big the whole design gets and how much memory and resources you use in your design.

Best regards,
/Farhad Abdolian