This is a pretty big project and you definitely need some IPs for the TFT and noise calculation or else you will spend a lot of time designing those.
The steps you mentioned sound OK but needs many more steps in between before you are done.
You can choose to do everything in parallell which will take a lot of resources on t he FPGA or design in pipeline which means more complicated data flow but smaller area.
If you do not need to do this in real time, I would suggest you go for Altera based FPGA, use the Freely available Nios processor and perform the TFT and noise calculation in SW, this way the complexity of your design will be minimum when it comes to actual FPGA design. But if you insist on using Xilinx, then you have steep time consuming road ahead of you.
Just my 2c,
Best regards,
Farhad Abdolian