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Avalanching an emitter does hot carrier injection at low current for Vio / Iib drift beyond spec, can "zener zap" aluminum through the junction at a hundred mA for a hard fail and you can't make a 40V ESD clamp (common mode range) protect a 7V Bvebo NPN worth a damn and it'd double the die area before it got close to effective. Most linears of this vintage did not really concern themselves with ESD as we define it today, but took care over application "expected abnormal conditions" such as exceeding input differential voltage for some fault or poor design.
The cross clamping allows safe operation at moderate overrange if the user puts limiting resistors on the inputs (app note / ref design)?
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The back diodes can also greatly improve prop delay, because the PNP emitters can pull but not push so in the LH direction response to a large step would be "soggy" without them.
An older datasheet shows a slightly different structure
It avoids the input short involved with the circuit shown in post #1. Notice that most of the differential input voltage appears at Q2 respectively Q3 BE junction, so it has to be designed with a much higher breakdown voltage than standard transistors.
It's probably that the inputs are substrate PNPs and the diff pair, lateral PNPs. Both of these built with C-B junctions that can take 40V. In which case the diodes are probably about switching speed than protection.