I would not look to stb analysis as a guarantee of suitable
operation, for ICMR design:spec closure.
Small signal analysis doesn't tell you things like, are you
clipping to the point that output distortion and gain-
falloff have made the application-circuit outcome useless.
If by "input common mode range" you mean the range
across which the device meets -all- data table performance
limits, that wants a lot more wringing-out. Things like gain,
PSRR, CMRR all get a lot worse when you are against the
rails, input or output, unless you have cute stuff like
beyond-the-rails internal charge pump fed supplies or
a double-everything rail-rail input architecture (output,
still doesn't like the final FETs going linear-region much).
Simulating response is easy. Asking the right questions
and appropriately criticizing the setup and the outcome,
that's more exhausting and tricky (you can make it easy
on yourself and hard on the eventual user, or vice versa).
Of course if there is no actual user and only one
parameter of interest, things get a lot simpler. I'd still
go with inspection of large signal time domain results
in an application-realistic testbench if it were me.