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Hi. I would like to design an input buffer to drive a 7bit ADC for 0.8Vppd input signal for up to 35MHz input at 0.9V supply. Can anyone suggest a suitable architecture? Thanks.
Sampling time shouldn't affect OPAmp parameters if you have a maximum input frequency of 40MHz (actually it will, probably coupling from sampler will occur to input, but you haven't shared how the sampling stage looks like and why you want an OPAmp).