Input buffer for ADC architecture for 35MHz signal bandwidth with 0.8Vppd swing with 0.9V Vdd .

[Ans5671]

Hi. I would like to design an input buffer to drive a 7bit ADC for 0.8Vppd input signal for up to 35MHz input at 0.9V supply. Can anyone suggest a suitable architecture? Thanks.

 

[Ans5671]

Hi, I am wanting to design an input buffer for a7 bit ADC with a sampling frequency of 2GSps. Max signal frequency = 40MHz. How to decide the specs of the op-amp (Av, input referred noise, settling time, Ugb, f3db, slew rate etc) to build a unity gain buffer.

 

[frankrose]

browse for a rail2rail input/output opamp circuit, there aren't too many.
At least 40MHz UGBW is OK, I would use a bit higher because of slewing, but too much higher is not recommended because of noise aliasing. 2GSPS is quite overkill.
you should rather know I/O impedances, non-linearity requirements. Noise with 7bit is not really a point I guess.

 

[Ans5671]

Thank you for your response @frankrose . It's actually a SAR ADC with a 250ps sampling time. So, how do the parameters such as sampling time, Input frequency and resolution etc affect the op-amp specifications?

 

[sutapanaki]

For a 7 bit resolution and 1GHz Nyquist frequency, you are probably better off to go with just a source follower. You can't get the frequency behavior with a feedback circuit as an opamp.

 

[Ans5671]

@sutapanaki
Thank you for your response. I would appreciate if you could back up your answer with a little explanation on how to determine the required op-amp bandwidth based on the ADC specs. I am trying to understand the design process as well. Why/why cannot I use a particular architecture.

 

[Taihung]

Because slew rate will come higher and higher when input frequency higher.
Normal opam will not use in this case because its bandwidth is too low (often few Mhz).
ADI call it driver, mean stronger ...
And higher speed will use differential amplifier to remove input offset current, common mode rejection, ..

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Another reason is swing voltage, larger range will make amplifier hot and some parameter drift, lower bandwidth...
You can take a look these useful books:

Linear Circuit Design Handbook, 2008 | Education | Analog Devices

Linear Circuit Design Handbook, Edited by Hank Zumbahlen, Published by Newnes/Elsevier, 2008, ISBN-978-0-7506-8703-4 (Also published as Basic Linear Design, Analog Devices, 2007, ISBN-0-916550-28-1).Fundamentals and applications of data acquisition components. Contains much of the material...

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High Speed System Applications, 2006 | Education | Analog Devices

High Speed System Applications, Edited by Walt Kester, Analog Devices, 2006, ISBN-1-56619-909-3.This is the third seminar book on the topic of high speed systems. Section 1 of this seminar book gives a brief overview of popular high speed converter architectures and how specific applications...

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[frankrose]

Thank you for your response @frankrose . It's actually a SAR ADC with a 250ps sampling time. So, how do the parameters such as sampling time, Input frequency and resolution etc affect the op-amp specifications?

Sampling time shouldn't affect OPAmp parameters if you have a maximum input frequency of 40MHz (actually it will, probably coupling from sampler will occur to input, but you haven't shared how the sampling stage looks like and why you want an OPAmp).

I have already written what you need to consider:
- IO voltage and supply range -> browse for rail2rail IO OPAmp
- IO impedances -> how much impedances the OPAamp has to match
- linearity requirements up to 40MHz -> SINAD of the sytem?

 

[Ans5671]

@frankrose Thank you again for your response. The sampling stage is a Gate boosted switch followed by 80fF cap. and I need to drive this S&H with a 0.8V differential signal using 0.95V supply circuits. So, to design a fully differential unity gain circuit i would like to use an op amp.

But biasing the circuit is not coming out to be feasible as VoCM = 0.475. and the input stage requires ViCM,min = Vt + 2 Vdsat ~ 0.6 referenced to ground and 0.3 referenced to supply. I guess this is out of bounds.
and the input CM range do no overlap, so even N-P complementary stage is out of option.

Sinad required is 7bit ~ 44dB.

 

[sutapanaki]

I actually haven't noticed in the original message the 40MHz limit for the input signal. 40MHz is well within the capabilities of an opamp. However, your track-sample period is only 500ps and with the transients caused by the sample, which need to settle within 500ps to 7bit accuracy, or even 8 bit, I think opamp will still not going to cut it in terms of BW and slew rate.