Input and Output delay budgeting for 2 FPGA

[cherjier]

input delay fpga

Hi all,

example i have 2 fpga on a single PCB board. fpga1 and fpga2 will communicate to each other. a signal will output from fpga 1 to fpga 2. so the output from fpga1 will actually have internal routing delay+ the board level routing delay, so how aftually we specified the expected input delay for fpga 2? does this information can ge get from the xilinx PAR report? or trace report?

any document regarding to this issue?

thank you very much

 

[echo47]

fpga input and output delay constraints

I can't give specific info without knowing the details of your signal path. Can you show a simple HDL example that illustrates what you are trying to do?

If you want to know the I/O performance capabilities of the FPGA, look in the "Switching Characteristics" section of your FPGA data sheet.

If you want to learn how to constrain the timing between internal logic and I/O pads, see chapter "Timing Constraint Strategies" in the ISE Constraints Guide.

If you want to know the maximum delays between your internal logic and I/O pads, the Trace Report gives that info, if you have applied suitable timing constraints to the signal. You may need to enable Trace's "verbose" mode to see info on signals that meet timing. Also, see the Trace manual in your ISE Development System Reference Guide.

If you want to see individual route delays, you can use the Tools -> Delay feature in FPGA Editor.

For most users, it is sufficient to apply suitable timing constraints, and if PAR meets those constraints, then you are done. If PAR has trouble meeting a constraint, then the Trace Report is helpful for locating the problem.