Inout verilog port and testbench

[Araxnid]

Hello, can someone help me with simulating my module, i read some topics here about this problem, but still cant understand how to use inout port in right way.

So i have a main module with USB_DATA inout type

inout	[7:0]USB_DATA;

then, i use

assign USB_DATA = RX_START ? Q : 8'bZ;

RX_START - my control signal ( reg ) and Q is reg[7:0]

So, in test bench i write it so:

	wire[7:0] USB_DATA;
	reg [7:0]USB_DATA_reg;
	
	reg oe = 0;

	
	USB U0(RESET,
	CLK,
	USB_DATA,
	USB_RD,
	USB_WR,
	USB_TXE,
	USB_RXF
	);
	
	assign USB_DATA = oe? 8'bZ : USB_DATA_reg;

	initial
	begin
	   USB_DATA_reg[7:0]=0;
		CLK = 0;
		RESET = 0;
	end

So, in modelsim i get USB_DATA_reg zero, but USB_DATA still X, what im doing wrong?

 

[FvM]

what im doing wrong?

Can't be seen from your testbench snippet. Most likely USB_DATA is driven from the module side too. But the state of most control signals is unknown. If they are right, the module may still act wrong.

 

[Araxnid]

Ok, i find my trouble - i didnt write anything to reg RX_START, so it was X from the simulation start and everything goes bad .I wrote zero to it and all go OK!
Sorry for trouble, and thanks for answering