Inout port problem in verilog test bench

[bhatnidhibhat]

Hi all,
This is the very old problem which is already discussed in this board. But still i didn't get the clear understanding. Please help me in this regard. I have written a verilog code for one of the bi-directional IO cell. It contains one core input A, one control pin CNTL, one inout pin Y and one output pin Z. Here Y will be operated both in driver mode and receiver mode.

When CNTL=0, A will be input and Y will be output. And Z will follow the Y.
When CNTL=1, driver will be disabled. i.e. through bufif0 i will make Y to tri-state.
In this case i want to use Y as a input and drive Z.

This is the simple and brief functionality of my IO cell. Now i want to write a verilog test bench for this code. I need to test it for both driver mode and receiver modes in single test bench.

Please let me know how to declare Y pin in tb and how to give the input to Y?

--
Shrinidhi.

 

[FvM]

The testbench pin should be of inout type as well and be tristated, when the connected D.U.T. pin is driving out and vice versa.
I don't see a general problem with this.

 

[nsingh95]

The testbench pin should be of inout type as well and be tristated, when the connected D.U.T. pin is driving out and vice versa.
I don't see a general problem with this.

Hi ,
use it as tri signal.

 

[bhatnidhibhat]

But in test bench we never use inout right? Either it should be reg or wire right?

Making tri-state means, whenever i am giving input to Y, i need to keep CNTL=1 right? That i have did. Still i will get Y=U throughout my simulation

 

[nsingh95]

But in test bench we never use inout right? Either it should be reg or wire right?

Making tri-state means, whenever i am giving input to Y, i need to keep CNTL=1 right? That i have did. Still i will get Y=U throughout my simulation

Hi,
If tri doesn't work then the only option is to write some logic for it.
Please check the attached doc for logic.

 

[bhatnidhibhat]

Hi..
Thanks for the doc. Will try and let u know the result. If i still face the problem, will provide my test bench. Then u may get more clear picture.

Regards,
Shrinidhi.