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| entity arch_D IS
GENERIC (N : INTEGER := 16);
Port ( clk,en_ref : in STD_LOGIC;
valid,ref_end : out STD_LOGIC;
byte_out : out STD_LOGIC_VECTOR (7 downto 0));
end arch_D;
architecture Behavioral of arch_D is
COMPONENT comp_A is
GENERIC (N : INTEGER := 16);
Port ( clk,en : in STD_LOGIC;
b0 : in STD_LOGIC_VECTOR(N*N/4-1 downto 0);
valid : in STD_LOGIC := '0';
b1 : out STD_LOGIC_VECTOR (N*N/4-1 downto 0));
end COMPONENT comp_A;
COMPONENT comp_B is
GENERIC (N : integer := 16);
Port ( clk,en : in STD_LOGIC;
b0 : in STD_LOGIC_VECTOR(N*N/4-1 downto 0);
valid : in STD_LOGIC := '0';
b1 : out STD_LOGIC_VECTOR (N*N/4-1 downto 0));
end COMPONENT comp_B;
-------SIGNAL Declaration----
signal b0,b1,b2 : STD_LOGIC_VECTOR(N*N/4-1 downto 0);
begin
compA : comp_A GENERIC MAP (N) PORT MAP (clk,en,b0,valid,b1);
compB : comp_B GENERIC MAP (N) PORT MAP (clk,en,b0,valid,b2);
mux : mux PORT MAP (b1,b2,sel,b0);
end Behavioral; |