inout pin with bidir port? (VHDL)

[toninlg]

port vhdl

I would like to use in VHDL an inout pin with a bidir port, but that doesn't work. There is always logic contention when I simulate it with Quartus.
I would like to send a data to the block if "write" is enabled and read it back if "read" is enable. How could I make it whit the bidir port? The only way I've found is to use an inout pin connected to the block by to way : as an input port and output port.

Thanks a lot.

 

[maksya]

I would like to use in VHDL an inout pin with a bidir port, but that doesn't work. There is always logic contention when I simulate it with qu(at)rtus.
I would like to send a data to the block if "write" is enabled and read it back if "read" is enable. How could I make it whit the bidir port? The only way I've found is to use an inout pin connected to the block by to way : as an input port and output port.

Thanks a lot.

Try this code:

LIBRARY IEEE;
    USE IEEE.std_logic_1164.all;

ENTITY bidirectional IS
PORT(   direction : in std_logic;
            input : in std_logic;
           output : out std_logic;
     input_output : inout std_logic);
END bidirectional;

ARCHITECTURE rtl OF bidirectional IS
BEGIN

output <= input_output;

process(input,direction)
begin
if (direction = '1') then
	input_output <= input;
else
	input_output <= 'Z';
end if;
end process;

END rtl;

 

[Resistance]

Hi ,
Yeah i saw one solution.. that will help but using buffer data type is a good design practice..

regards

 

[toninlg]

Using a buffer for the output?

 

[yming]

buffer mode indicates a port which can be used for both input and output, and it can have only one source.

inout mode indicates a port which can be used for both input and output.

 

[toninlg]

I've done the following code. If CS=0 and WR=0 data is stored. If CS=0 and RD=0 the written data is read back. The output is updated at the falling edge of INT.
What do you think of it?

LIBRARY ieee;
USE ieee.std_logic_1164.all;

--  Entity Declaration

ENTITY comp IS
	PORT
	(
		clock_20MHz : IN STD_LOGIC;
		CS : IN STD_LOGIC;
		WR : IN STD_LOGIC;
		RD : IN STD_LOGIC;
		INT : IN STD_LOGIC;
		scmpr : OUT STD_LOGIC_VECTOR(6 downto 0);
		sens : OUT STD_LOGIC;
		data_in : INOUT STD_LOGIC_VECTOR(7 downto 0)
	);
END comp;


--  Architecture Body

ARCHITECTURE f OF comp IS

	signal data : STD_LOGIC_VECTOR(7 downto 0);
	
	BEGIN

	PROCESS(clock_20MHz,CS,WR,RD,data)
	
	BEGIN
	
			IF (WR='1' AND RD='0' AND CS='0') THEN
				data_in<=data;
				ELSE
					data_in<=(OTHERS=>'Z');
					IF (clock_20MHz'EVENT AND clock_20MHz='1') THEN
						IF (WR='0' AND RD='1' AND CS='0') THEN
							data<=data_in;
						END IF;
					END IF;
			END IF;
	END PROCESS;

	PROCESS (INT)
	
	   BEGIN
		IF (INT'EVENT AND INT='0') THEN
                	scmpr <= data (6 downto 0);
                 	sens <= data(7);
		END IF;
	   END PROCESS;
				
END f;

 

[toninlg]

Anybody to have a look at my code, to see if it's correct or if there are obvious programming errors? Simulating seems OK but I don't know if I have tried all possible situations.

Thanks a lot.