Initialize inputs of CPLD

[bubuta77]

Hi.
I am using EB of cool-runner II.
At my code i have some inputs connected to pins (by ucf file). When i start the value of inputs are undefined until some external signal will arrive and i want em defined always.
i don't want to use external resistors for pull up or pull down. I tried to set using the ucf file the pull-up mode operation for pins defined as inputs but it was unsuccessful (i don't measure 3.3V at this pins..)
I want to set my "in" pins as "inout" and using process to initialize them once:

initialize: process(clk)
begin
if flag=0 then
input<="00000";
flag<=1;
end if;
end process initialize;

it legal and/or common thing to do? will it works?

 

[FvM]

Weak pullup and similar CPLD properties are hardware features that have to be defined in vendor specfic constraint files or configuration tools. It can't be set in generic HDL, may be with vendor specific attributes.

I can confirm that Cool Runner II offers weak pull-ups according to data sheet. But I'm not using Xilinx and can't tell you how to enable it. I presume it's as simple as with other vendor's CPLDs.

 

[bubuta77]

i do set pull-up mode at ucf (constraint file) file according to Xillinx instructions:
NET "input<0>" PULLUP;
but it doesn't work for me.
Setting input as inout do work and enable me to define inputs but i am wondering if it good technique or not...

Weak pullup and similar CPLD properties are hardware features that have to be defined in vendor specfic constraint files or configuration tools. It can't be set in generic HDL, may be with vendor specific attributes.

I can confirm that Cool Runner II offers weak pull-ups according to data sheet. But I'm not using Xilinx and can't tell you how to enable it. I presume it's as simple as with other vendor's CPLDs.

 

[FvM]

Setting input as inout do work and enable me to define inputs but i am wondering if it good technique or not...

If you mean the code snippet in your initial post, it will set an inout port to all zero and never allow to read it as an input again before you assign 'Z' state to it. As said, weak pull-up function in hardware can't be synthesized from HDL code.