Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

initialising a std_logic signal

Status
Not open for further replies.
K

kcinimod

Member level 3
Joined
Dec 19, 2011
Messages
63
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,714
Code: 
library ieee;
use ieee.std_logic_1164.all;
    
entity counter is
    port( 
        clk_in : in std_logic;
        data : in std_logic;
        enable : in std_logic;
        dout : out std_logic        
    );
end counter;

architecture count of counter is

signal data_sync : std_logic_vector(1 downto 0);
signal pre_count : integer;
signal pre_count_1 : integer;
signal pre_count_2 : integer;
signal data_count : integer;
signal trigger : std_logic;

begin
    process(clk_in)
    begin
        if rising_edge(clk_in) then
            data_sync <= data_sync(0) & data;
        end if;
    end process;

    count_proc : process(clk_in)
    begin
        if rising_edge(clk_in) then
            if enable = '0' then
                data_count <= 0;
                pre_count <= 0;
                pre_count_1 <= 0;
                pre_count_2 <= 0;
				trigger <= '1';
            elsif (data_sync(1) = '1') then
                if (data_count = 0) then
                    pre_count <= 0;
                    data_count <= data_count + 1;
                elsif (data_count = 1) then
					if (pre_count > 5) then
						pre_count_1 <= pre_count;
						data_count <= data_count + 1;
					end if;
                elsif (data_count = 2) then
					if (pre_count > 5) then
						pre_count_2 <= pre_count;
						data_count <= data_count - 1;
					end if;
                end if;
                pre_count <= 0;
            else
                pre_count <= pre_count + 1;
            end if;
        end if;
    end process;
    
    compare_proc : process(clk_in)
    begin
        if rising_edge(clk_in) then
            if (data_count = 1) then
                if (pre_count_1 > pre_count_2) then
                    dout <= '1';
					trigger <= '0';
                elsif (pre_count_1 < pre_count_2) then
                    dout <= '0';
					trigger <= '0';
                end if;
			else
				trigger <= '1';
            end if;            
        end if;
    end process;
end count;

hi all, for the above code, when enable is '0', it will initialise trigger to '1', however when i do this, the trigger signal during is simulation is as shown in the pic Untitled.png the trigger appear with X.

however, when i remove the trigger <= '1' from the code, it appears correctly Untitled.png

may i know why is this so ?
 

kcinimod said:
Code: 
library ieee;
use ieee.std_logic_1164.all;
    
entity counter is
    port( 
        clk_in : in std_logic;
        data : in std_logic;
        enable : in std_logic;
        dout : out std_logic        
    );
end counter;

architecture count of counter is

signal data_sync : std_logic_vector(1 downto 0);
signal pre_count : integer;
signal pre_count_1 : integer;
signal pre_count_2 : integer;
signal data_count : integer;
signal trigger : std_logic;

begin
    process(clk_in)
    begin
        if rising_edge(clk_in) then
            data_sync <= data_sync(0) & data;
        end if;
    end process;

    count_proc : process(clk_in)
    begin
        if rising_edge(clk_in) then
            if enable = '0' then
                data_count <= 0;
                pre_count <= 0;
                pre_count_1 <= 0;
                pre_count_2 <= 0;
				trigger <= '1';
            elsif (data_sync(1) = '1') then
                if (data_count = 0) then
                    pre_count <= 0;
                    data_count <= data_count + 1;
                elsif (data_count = 1) then
					if (pre_count > 5) then
						pre_count_1 <= pre_count;
						data_count <= data_count + 1;
					end if;
                elsif (data_count = 2) then
					if (pre_count > 5) then
						pre_count_2 <= pre_count;
						data_count <= data_count - 1;
					end if;
                end if;
                pre_count <= 0;
            else
                pre_count <= pre_count + 1;
            end if;
        end if;
    end process;
    
    compare_proc : process(clk_in)
    begin
        if rising_edge(clk_in) then
            if (data_count = 1) then
                if (pre_count_1 > pre_count_2) then
                    dout <= '1';
					trigger <= '0';
                elsif (pre_count_1 < pre_count_2) then
                    dout <= '0';
					trigger <= '0';
                end if;
			else
				trigger <= '1';
            end if;            
        end if;
    end process;
end count;

hi all, for the above code, when enable is '0', it will initialise trigger to '1', however when i do this, the trigger signal during is simulation is as shown in the pic View attachment 70492 the trigger appear with X.

however, when i remove the trigger <= '1' from the code, it appears correctly View attachment 70493

may i know why is this so ?
Click to expand...

Buddy, two different process clk assignemts of trigger for one same signal. This is not accepted in tools\language. Your simulator was right, you cannot drive same register at two different process even though with same clock.

It is a bad driver logic, since you are driving the same FF with two clocks(Even it is same clock, the tool is blind :) in this case)
For solving this, use a buffer to pass the values.....

And by the way what is the purpose of the circuit?.
Also replace this statement
Code: 
elsif (pre_count_1 < pre_count_2) then

with
Code: 
else

Cheers
 

the purpose of the circuit is to compare two adjacent time interval and output a 1 or 0 base on the results, the trigger is a signal for another circuit to tell it when to send the data out(sends data on falling edge of trigger)

if i replace
Code: 
elsif (pre_count_1 < pre_count_2) then

with
Code: 
else

it will include pre_count_1=pre_count_2, i require it to do nothing when its equal
 

hi,

Why can't you remove the trigger <= '1'; from the count_proc process and include it in the compare_proc process..

Which is the right way...

Otherwise trigger will get multiple assignment and goes to unknown..

You can assign the trigger only in one process...

You can use the enable in the compare_proc process means when the enable is zero under any condition assign the trigger value as '1'
 

Mmm...you can redesign it this way...
Code: 
 if rising_edge(clk_in) then
            if (data_count = 1) AND enable = '1' then
                if (pre_count_1 > pre_count_2) then
                    dout <= '1';
					trigger <= '0';
                elsif (pre_count_1 < pre_count_2) then
                    dout <= '0';
					trigger <= '0';
                end if;
			else
				trigger <= '1';
            end if;
Remove the assignment to trigger <= '1' in compare_proc
From your code, I could see your data_count will never become 0 until enable is zero. So this should solve.

Also use a reset for all of your design, it is a good practice.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top