initialization ram vhdl
You can create a large asynchronous RAM by using distributed RAM. Refer to section "RAMs and ROMs HDL Coding Techniques" in your XST User Guide, and search for the word "distributed" or "asynchronous".
You can also use Core Generator to create distributed RAM. Browse the "Basic Elements - Memory Elements" section. I don't recall which core is the best choice.
However, a large distributed RAM consumes a lot of logic fabric, and it takes a while to synthesize, and it will perform rather slowly. If possible, try to modify your project so it can use the much nicer synchronous BRAMs.
You don't have to add logic to your FPGA design just to initialize the RAM with zeros or some constant data. The FPGA configuration process can initialize the RAM for you. There are various way of specifying your desired initialization data, such as by using HDL initial statements or attributes, or core generator initialization files. Some of these methods are shown in the"RAMs and ROMs HDL Coding Techniques" section.