entity cdr_rx is
generic (
DIn_Width : integer := 8;
DOut_Width : integer := 10 -- Width of dout
);
port (
Rst : in std_logic;
RefClk : in std_logic;
Sin : in std_logic;
Data_Out : out std_logic_vector (DOut_Width-1 downto 0);
DOut_Valid : out std_logic;
Sample_Error : out std_logic;
PLL_Lock : out std_logic;
SClk : out std_logic;
SClk90 : out std_logic;
LowClk : out std_logic
);
attribute dout : string;
attribute din : string;
attribute dout of SClk : signal is "";
attribute din of RefClk : signal is "";
attribute dout of SClk90 : signal is "";
end cdr_rx;
architecture arch_cdr_rx of cdr_rx is
-- -------------------------------------------------------------------------------------
-- Constant definitions
--
-- -------------------------------------------------------------------------------------
-- Component definitions
--
component Ser2Par
generic (
DOut_Width : integer
);
port (
PLL_Lock : in std_logic;
Rst : in std_logic;
SIn : in std_logic;
SClk : in std_logic;
SClk90 : in std_logic;
RefClk : in std_logic;
DOut : out std_logic_vector (DOut_Width-1 downto 0)
);
end component;
component Data_Extract
generic (
DIn_Width : integer := 8;
DOut_Width : integer := 10;
Lock_Number : integer := 4;
Max_Samples_per_Word : integer := 4
);
port (
Rst : in std_logic;
Clk : in std_logic;
DIn : in std_logic_vector (DIn_Width-1 downto 0);
DOut : out std_logic_vector (DOut_Width-1 downto 0);
DOut_Valid : out std_logic;
Sample_Error : out std_logic
);
end component;
component Rx_Dyn_PLL
port (
CLK : in std_logic;
RESET : in std_logic;
CLKOP : out std_logic;
CLKOS : out std_logic;
CLKOK : out std_logic;
LOCK : out std_logic
);
end component;
-- -------------------------------------------------------------------------------------
-- FSM state variable assignments
--
-- -------------------------------------------------------------------------------------
-- Signal definitions
--
signal data_4x : std_logic_vector (DIn_Width-1 downto 0);
signal data_sampled : std_logic_vector (DOut_Width-1 downto 0);
signal Lock : std_logic;
signal DOut_Valid_Int: std_logic;
signal RxClk : std_logic;
signal SClk_Int : std_logic;
signal SClk90_Int : std_logic;
signal LowClk_Int : std_logic;
signal Data_D4 : std_logic_vector (DOut_Width-1 downto 0);
signal Cnt : natural range 0 to 4;
-- -------------------------------------------------------------------------------------
-- Attributes settings
--
-- -------------------------------------------------------------------------------------
-- Begin of Architecture description
--
begin
U1 : Ser2Par
generic map (DOut_Width => 8)
port map(
PLL_Lock => Lock,
Rst => Rst,
SIn => SIn,
SClk => SClk_Int,
SClk90 => SClk90_Int,
RefClk => RxClk,
DOut => Data_4x);
U2 : Data_Extract
generic map (
DIn_Width => 8,
DOut_Width => 10,
Lock_Number => 4,
Max_Samples_per_Word => 4)
port map(
Rst => Rst,
Clk => RxClk,
DIn => Data_4x,
DOut => Data_Sampled,
DOut_Valid => DOut_Valid_Int,
Sample_Error => Sample_Error);
U3 : Rx_Dyn_PLL
port map(
CLK => RefClk,
RESET => Rst,
CLKOP => SClk_Int,
CLKOS => SClk90_Int,
CLKOK => LowClk_Int,
LOCK => Lock);
process (SClk_Int, Rst)
begin
if Rst = '1' then
RxClk <= '0';
elsif rising_edge(SClk_Int) then
RxClk <= not RxClk;
end if;
end process;
...
I use resets on all of my processes (or most anyhow), except actual state machine. (in the "case" part..; however, you can initialise the Present_State to a specific state in the reset of the process).
This is where i define my initial values.
Also, most resets are not synchronous. That's why it's outside the clock region.
process (clk, rst)
begin
if rst = '1' then
CurrentState = S0;
elsif rising_edge (clk) then
CurrentState <= NextState;
end if;
end process;
process (CurrentState)
case CurrentState is
when S0 =>
...
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