Initial Statement in Verilog: Blocking or Non Blocking

[kunal1514]

Can any body tell me which is better in Initial Statement in Verilog

Blocking or Non Blocking

also in Task which is better.

 

[ankit12345]

Initial Statement

That depends upon what type of logic u want to impliment.

If u want to use the updated values which r caluculated in side the initial to compute other signals in initial,then u have to use blocking,
the same is true for both.

I think the simulator performence differs for blocking and non blocking....... comments please

 

[incisive]

Re: Initial Statement

If

the testcase/testbench is as such

for Initializing DUT I/P Values
initial begin
a = 0;
b = 0;
c = 0; // Use Blocking Statements
end


for writing a test case

initial begin
@(posedge CLOCK)
begin
a <= 1'b1;
b <= 1'b0; // Use Non-Blocking statements.
c <= 1'b0l;
end

 

[vlsi_whiz]

Re: Initial Statement

The initial statement is not synthesizable. It is used only in simulation. In the testbench, initial statement is used to force the initial test cases for a simulation,ie, when the simulation starts what values the signals drive is determined by the initial statement.

It is always better to use non-blocking statements in the initial block as we want all the signals in the initial block to get their initial values when simulation starts. You can also use blocking statements to determine the order in which the signals get their initial values.

 

[sumit_techkgp]

Initial Statement

It all depends on what u want
Sumit

 

[learnbydo]

Initial Statement

I think non-blocking is better.
All variable is assigned at the same simulation step.