Information about set up and hold constraints

[pandit_vlsi]

hi all.
i know what is set up and hold constaints.
but i want to know
1.why these timings are to be satisfied.?
2.Which part/factors of the F/F rule these timings?.
3.how these timings are calculated for a F/F?.

plz explain...



regards,
Pandit.

 

[eda_boy]

Re: set up and hold.

Hi,
Setup and hold timing conditions are to be verified to ensure that correct values are stored in the FF.
Setup and hold times for a FF depend on its implementation. A detailed method to calculate the setup and hold time is provided in Digital Integrated Circuits by Jan M Rabaey.
EDA_BOY

 

[anilkumarv]

Re: set up and hold.

Setup and hold times are to be satisfied so that there is no setup violation and hold violation respectively.If setup violation occurs then it will result into race condition which in turn results in loss of data

 

[Karthi]

Re: set up and hold.

hi,
Meeting the setup and hold timing of a Flip-Flop ensures that correct data is sampled by the clock. U must be knowing that violating these requirements can lead to metastability. These timings depends on the implementation of the flip flop and also on the clock transition, input data transition.

 

[zhangpengyu]

set up and hold.

Its for data sample,if the timing is not meet,then data is sampled error!

 

[praveen_venigalla]

Re: set up and hold.

Setup & Hold is for a flop to capture stable value at its input.

for a flop its input may come from direct input ports of a chip or from output of another flop through combinational logic.

your signal must be stable at the input of a flop either it is coming from any source.

Praveen.

 

[yrpavankumar]

set up and hold.

Setup time is the time required to charge the input capacitance of the FF (D input) to a correct logic (i.e to VDD for logic-1 and VSS for logic-0).

Hold time is required to for two reasons
1. to take care of clock skew effect.
2. to allow the internal nodes of FF to charge/discharge to correct voltage levels.

Both the conditions have to be satisfied for correct sampling of data else output of FF will go to metastable condition.

 

[giri_lp]

Re: set up and hold.

The sequential nature of the flip flop makes it to depend on the clock signal and it never can respond instantaneously... Hence it needs some time to get back and that is set up time...

the last part can be answerd by referring to the circuit's nature and it's response time...

 

[mpkp123]

Re: set up and hold.

Just see the Flip dflops topic in Moris Mano book.
I think it will be clear to you then.

 

[ramana_k22]

Re: set up and hold.

Hi,
Setup Time is needed latch the data from the input to output. Hold Time is required to make sure that data sent to next block is correct data. Setup Time is Tclkmin - Tcomb - Tclkq. Thold < Tclkq
regards,
ramana