#### sina_extreme

##### Junior Member level 2

i have written this code in activeHDL and it worked flawlessly when simulating

but I cant synth it correctly

here is the code

Code:

```
module reciever ( clock ,reset ,in ) ;
input clock ;
input reset ;
input [7:0] in ;
parameter W=8'h08 ; parameter B=8'h08 ;
parameter A1=8'hf6 ; parameter A2=8'h28 ;
reg [B:0] mem [0:W] ;
reg [2:0] state ;
reg [2:0] next_state ;
reg [7:0] temp ;
reg flag ;
reg [4:0] i ;
reg idl ;
reg [B:0] number_of_ones [0:W] ;
reg [3:0] number_of_ones_counter ;
always @ (posedge clock)
begin
state = next_state ;
end
always @ (negedge clock)
begin
temp = in ;
if (state == 3'b000 | state == 3'b001 | state == 3'b010 )
begin
if (temp == A1) next_state = state + 1 ;
else next_state = 0 ;
end
else if (state == 3'b011 | state == 3'b100 | state == 3'b101 )
begin
if (temp == A2) next_state = state + 1 ;
else next_state = 0 ;
end
else if ( state == 3'b110 )
begin
next_state = state ;
flag = 1 ;
end
else next_state = 0 ;
end
always @ (posedge clock)
begin
if ( flag )
begin
mem[i] = in ;
for (number_of_ones_counter = 0 ; number_of_ones_counter < 8 ; number_of_ones_counter = number_of_ones_counter + 1)
begin
if (in[number_of_ones_counter]) number_of_ones[i] = number_of_ones[i] + 1 ;
else number_of_ones[i] = number_of_ones[i] ;
end
if ( i < 5'h9 ) i = i+1 ;
else i = 0 ;
end
else mem[i] = 0 ;
end
always @ (posedge clock)
begin
if ( reset )
begin
next_state = 0 ;
state = 0 ;
temp = 0 ;
flag = 0 ;
number_of_ones_counter = 0 ;
for ( i=0 ; i<9 ; i= i+1 )
begin
mem[i] = 0 ;
number_of_ones[i] = 0 ;
end
i = 0 ;
idl = 0 ;
end
else idl = 1 ;
end
endmodule
```

Code:

```
INFO:Xst:2679 - Register <state> in unit <reciever> has a constant value of 000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <temp> in unit <reciever> has a constant value of 00000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <next_state> in unit <reciever> has a constant value of 000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <flag> in unit <reciever> has a constant value of 1 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <flag> in unit <reciever> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <mem<0>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <mem<1>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <mem<2>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <mem<3>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <mem<4>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <mem<5>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <mem<6>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <mem<7>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <mem<8>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones_counter> in unit <reciever> has a constant value of 1000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones_counter> in unit <reciever> has a constant value of 0000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones<0>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones<1>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones<2>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones<3>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones<4>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones<5>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones<6>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones<7>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones<8>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <i> in unit <reciever> has a constant value of 00000 during circuit operation. The register is replaced by logic.
Synthesizing Unit <reciever>.
Related source file is "receiver.v".
WARNING:Xst:646 - Signal <mem> is assigned but never used.
WARNING:Xst:646 - Signal <idl> is assigned but never used.
WARNING:Xst:646 - Signal <temp> is assigned but never used.
Found 9-bit adder carry out for signal <CON
```

thank you for your attention