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INFO:Xst 2679 problem synthesising a code

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sina_extreme

sina_extreme

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hi people
i have written this code in activeHDL and it worked flawlessly when simulating
but I cant synth it correctly
here is the code
Code: 
module reciever ( clock ,reset ,in ) ;

input clock ;
input reset ;
input [7:0] in ;

parameter W=8'h08 ; parameter B=8'h08 ;
parameter A1=8'hf6 ; parameter A2=8'h28 ;

reg [B:0] mem [0:W] ;
reg [2:0] state ;
reg [2:0] next_state  ;
reg [7:0] temp  ;
reg flag  ;
reg [4:0] i  ;
reg idl  ;
reg [B:0] number_of_ones [0:W] ;
reg [3:0] number_of_ones_counter ;

always @ (posedge clock) 
   begin
      state = next_state ;
	end

always @ (negedge clock)
	begin
		temp = in ;
		if (state == 3'b000 | state == 3'b001 | state == 3'b010 )
			begin
				if (temp == A1) next_state = state + 1 ;
			    else next_state = 0 ;
			end		
		else if (state == 3'b011 | state == 3'b100 | state == 3'b101 )
			begin
				if (temp == A2) next_state = state + 1 ;
				else next_state = 0 ;	
			end
		else if ( state == 3'b110 )
			begin
				next_state = state ;
				flag = 1 ;
			end
		else next_state = 0 ;
	end

always @ (posedge clock)
	begin
	if ( flag )
		begin
			mem[i] = in ;
			for (number_of_ones_counter = 0 ; number_of_ones_counter < 8  ; number_of_ones_counter = number_of_ones_counter + 1)
				begin
					if (in[number_of_ones_counter]) number_of_ones[i] = number_of_ones[i] + 1 ;
					else number_of_ones[i] = number_of_ones[i] ;
				end					
			if ( i < 5'h9 ) i = i+1 ; 
			else i = 0 ;
		end
	else mem[i] = 0 ;
end	
always @ (posedge clock)
	begin
	if ( reset )
		begin
			next_state = 0 ;
			state = 0 ;
			temp = 0 ;
			flag = 0 ;
			number_of_ones_counter = 0 ;
			for ( i=0 ; i<9 ; i= i+1 )
				begin 
				mem[i] = 0 ;
				number_of_ones[i] = 0 ;
				end
			i = 0 ;
			idl = 0 ;
		end
	else idl = 1 ;
    end
	
endmodule
this is the warning i receive when synthing
Code: 
INFO:Xst:2679 - Register <state> in unit <reciever> has a constant value of 000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <temp> in unit <reciever> has a constant value of 00000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <next_state> in unit <reciever> has a constant value of 000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <flag> in unit <reciever> has a constant value of 1 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <flag> in unit <reciever> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <mem<0>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <mem<1>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <mem<2>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <mem<3>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <mem<4>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <mem<5>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <mem<6>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <mem<7>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <mem<8>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones_counter> in unit <reciever> has a constant value of 1000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones_counter> in unit <reciever> has a constant value of 0000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones<0>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones<1>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones<2>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones<3>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones<4>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones<5>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones<6>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones<7>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <number_of_ones<8>> in unit <reciever> has a constant value of 000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <i> in unit <reciever> has a constant value of 00000 during circuit operation. The register is replaced by logic.

Synthesizing Unit <reciever>.
    Related source file is "receiver.v".
WARNING:Xst:646 - Signal <mem> is assigned but never used.
WARNING:Xst:646 - Signal <idl> is assigned but never used.
WARNING:Xst:646 - Signal <temp> is assigned but never used.
    Found 9-bit adder carry out for signal <CON
could you please help me out here
thank you for your attention
 

That's strange. I took a brief look and failed to see the problem. Waiting for someone more attentive to find it :)
 
FYI i used Xilinx ISE for synthesising
the simulation results were positive in activeHDL
but i couldn't synth them using xilinx ISE program
 

Too bad I don't know Verilog that well.
I was once told you shouldn't use = for assigning values to registers, but rather <=. Could that be the problem?

---------- Post added at 16:36 ---------- Previous post was at 16:34 ----------

P.S. I've got completely another bunch of warnings. I'll try to sort them out.

---------- Post added at 16:39 ---------- Previous post was at 16:36 ----------

OK, I got it.
Your module has no outputs :)
 
about the <= I am almost sure that it doesn't really matter
I added an output to my code but still receive the wired warnings
what should I exactly change in the code ?
 

i made some small configuration in the circuit
now it has an output port that relays the input if flag == 1
some other problems were solved but this INFO:Xst 2679 thing still exists
 

If I understand correctly, that still won't solve your problem.
You don't just need a formal output. You NEED to make an output whatever signal you want to produce.

I'll give an exapmple. Let's say your module has 3 inputs: A,B,C and an output O. Let's then say you do like this:
result = A + B;
O = A;

Wil this simulate? Sure. Will this synthesise? Only O = A. Why? Because without assigning A+B to output you have no way of further using it, and thus it will be trimmed as unused.
 
hi again thanks for the advise but it didn't work eighter
if introduced a net called stateprime as an out put and then assigned the value of state to it
like this : assign stateprime = state ;
but still I receive the same massage that "INFO:Xst:2679 - Register <state> in unit <reciever> has a constant value of 000 during circuit operation. The register is replaced by logic."
 

I've got an impression your output should NOT be state. It should be the final result the code is computing. Only that will ensure everything is synthesised properly.
 
hi...
is their any errors you are getting or only the warnings?
 

no errors however when i tried to put some outputs to my code an error appeared saying that the register flag is driven from multi sources
beside that there are no errors and just 3 warnings as i have already attached them on my first post
 

hi again
even i am new to verilog but i was able to reduce that info by adding "assign keyword"
first run your program and see how many info you have in design summary it will be showing you 27 then change line
temp = in ; in your code to "assign temp = in ;"
i will reduce again and see the result in design summary it will reduce to 26
again change in your code line
mem = in ; to "assign mem = in ;"
more check other things..
 
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