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infineon PEF2256 E1 transceiver and FPGA board

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Feb 26, 2009
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E1 transceiver and FPGA

i am using infineon PEF2256 E1 transceiver in my project and i want to interface it with my FPGA board. i want to configure the IC to handle SS7 signaling...i have read its datasheet and i have some idea about the pins but still im confused..

can anyone help me with this whole situation ?

Re: E1 transceiver and FPGA


I also want to begin to develop something on e1 but I have little idea of how, by what I see is a frame and a LIU, and would not need to attack the line more and work with E1 frame. Right?. This chipset is only for one line. Right?, no quad. Approximate price that has this chipset?.

does anyone have any examples of vhdl or verilog to see how to attack this chipset? If I find some information, I put in this thread ;-)


Re: E1 transceiver and FPGA


any idea or code? thanks !


Re: E1 transceiver and FPGA

i've got idea , like we'll connect FPGA on one side and LDI on the other side. FPGA will fetch the data (MSUs) from E1 transceiver by issuing an address of the register where the MSU is stored. i'm looking into it in detail...lets c..


I am doing a project on G.703 (64Kbps) to E1 (2Mbps) conversion. The 64Kbps signal is readily available & my plan is to map this 64Kbps data into TS1 slot of E1 frame and extract the same at receiving end & vice-versa. While doing so I have found two IC's which can help me in doing my job:

1. Infineon: PEF2256.
2. Maxim: DS2155.

So, I'll need a little help in understanding the interface part of this IC's with intel or motorola processor (as it says in the datasheet). i.e., how do i interface this IC with processor & which processsor or controller should I use or do i have to use a dsp or fpga???
(Note: I dont want any software configurable part, simply map the 64kb data in to 2mb & extract it at the receiving end).

Thanks & Regards.

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