shaiko
Advanced Member level 5
I'm working on an asynchronous ( completely clockless ) design on on Actel Igloo FPGA.
To avoid race conditions, I'd like to inffer logic delays between signals:
delayed_a_signal <= a_signal ;
I want "a_signal" to be transffered to "delayed_a_signal" after a time delay.
How can I achieve this ?
To avoid race conditions, I'd like to inffer logic delays between signals:
delayed_a_signal <= a_signal ;
I want "a_signal" to be transffered to "delayed_a_signal" after a time delay.
How can I achieve this ?