Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Inductance of a Through Silicon Via with HFSS

Status
Not open for further replies.

cshah7

Newbie level 1
Newbie level 1
Joined
Oct 28, 2009
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Atlanta
Activity points
1,286
Hi,
Can anyone please help me for finding out the Inductance between two parallel cylindrical Through Silicon Vias used for 3-D Integration using HFSS?

The condition is that the flow of current through the TSV is in opposit direction and the dielectric separating them is Silicon substrate.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top