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inductance and capacitance

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masadi

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sonnet return path silicon

hi....

i read books about microstrip discontinuity, especially about bend(corner). can anybody explain me what can introduce inductance and capacitance?
in books "foundations of microstrip circuit design" , it said that inductance is the effect of "current flow interruption" , i still dont understand bout this statement.

thanks a lot
[/b]
 

wusen

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inductance(capacitance) means magnetic field(electric field) predominates near the discontinuity regions.
in the other word, when the microstrip discontinuity mainly lead to large current(like change the flowing direction), it introduce inductance, while lead to charge accumulation(like in terminal), it introduce capacitance.
 

masadi

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Ok i understand, but what kind of discontinuities that can lead to large current ( like change the flowing direction) ?
 

House_Cat

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I believe your problem is that you are trying to visualize the microstrip as a single layer trace on a circuit board.

The microstrip has two components - the trace that you place on the board to connect the signal source with the signal sink, and the return path for the signal. The return path is often a copper plane on the layer under the strip. The complete signal path is a loop consisting of the trace and the return path on the plane.

Anything that makes the loop larger, increases the inductance of the signal path. If you place a discontinuity such as a break in the plane, or a via that takes the signal to a different circuit board layer, the loop becomes larger. The return part of the signal has to travel a longer distance, and may be physically forced away from the area directly under the trace. That increase in the return side path length is the change of direction that your books are talking about.

Remember, think in terms of a complete loop - the signal path is not just a trace on one layer.

As a separate, but related, comment - a bend in a microstrip trace does not have a significant effect on signal integrity below about 10GHz. There are several research papers available, and it is discussed in many recent texts. A couple of easily found references are below:

http://www.edn.com/article/CA46858.html
http://www.montrosecompliance.com/Technical_papers/corners-Japan.pdf
http://www.ultracad.com/90deg.pdf
 

wusen

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House_Cat, In the viewpoint of PCB industry, you are right.
but in the electromagnetic & microwave society, i think there should be no exact path loop, because it is the excitations & boundary conditions -> field and current distribution. You can treat both the current in the conductor and the field in the dielectric as the signal path since they are related. So when there are even no gound below the trace(here it become a radiator), the signal path can be formed yet.

for conveniency, The circuit representation is introduced. the description of the essential characteristics of the discontinuity can be expressed in a reasonably small number of variables(i.e. in generall the discontinuity should be descrited in a equivalent network , not just introduce inductance or capacitance only).

i hope i had expressed clearly with my poor english.
 

House_Cat

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A radiator (antenna) also has a return path. Sometimes, it is called the 'antenna ground image'. In the world of electronics, ALL signals have a complete loop path - everything happens in complimentary pairs - otherwise you are creating and utilizing the energy, both kinetic and potential, from nothing.

A radiator (antenna) is nothing more than an impedance matching device to the next energy conveying medium.

Electrons cannot be created from thin air, nor are they destroyed in the process of moving through an electronic circuit. There must be a complete loop to utilize the energy of electrons for the purpose of doing work in an electronic circuit. Fields, both magnetic and electrostatic, are not just abstract concepts - they are real. The entire field of electronics is based on mathematic models of observed phenomena, it is not a science of theoretic predicted behavior. Faraday, Helmholtz, Maxwell, Hertz, Ohm etc. reported what they observed - they didn't theorize and then confirm.

If your mathematics describes only one side of the CIRCUIT - it is incomplete.
 

wusen

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Of course, the continuity equation which expresses the fact that charge is not created or destroyed must be obeyed.
But, to answer the question why introduce inductance and capacitance in the discontinuity, I think it can be interpreted in two approach though they are equivalent: In the field point, to satisfy the boundary condition in the discontinuity, high order mode EM field is excited, we can use equivalent inductance(L) and capacitance(C) and conductance(G) to describe these high order mode field though they can be neglected in lower frequency. In the current point, like in the bend of trace, the sharp corner will lead to: charge accumulation(->C), edge-current disturbance(->L) ,more current flow to the top of trace(->G).
Btw, your definition of antenna is incisive.
 

House_Cat

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I find no fault with your last statement. However, in the real world of practical circuits, the disturbances you cite are negligible. They are discussed in the two papers I posted above, as well as texts by Dr. Johnson, Montrose, Smith, and many others.

Understanding and demostrating the possilbilities with the mathematical tools is both important and useful; however, one needs to keep it all in perspective. Studying a grain of sand is useful to understanding the structure of a beach, but the presence or absence of that single grain does not keep the ocean in its bounds.

The inductive and capacitive effects at the right angle corner of a wire or circuit board trace are figuratively as small as that single grain of sand. There is even experimental evidence that as the frequency of the signal entering the right angle increases, the path taken by the wavefront moves more toward the inside of the bend - further away from the outside corner where the additional capacitance and inductive fringing are predicted by the mathematical model. This appears to be a result of the same field effects that give rise to the 'skin effect' at high frequency - the natural tendency of an electromagnetic wavefront to take the path of least inductance.

We could continue to 'milk the mouse', but the answer I gave above still stands. In real world situations, the complete loop formed by the signal path and its return is increased by discontinuities which force the return path to deviate from its natural tendency to remain directly adjacent to the signal path (the path of least inductance). When that loop is increased in size, the inductance is increased, and the result is signal distortion from reflection, and/or delay of edge high frequency components.
 

rautio

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Some good points raised above, but in spite of two decades of intense work in EM theory, I still go back to my microwave designer roots and I always look for a physically reasonable understanding that cuts through all the theory.

In the case of a micrsstrip bend, look at the bend as a short section of wierd transmsmission line. It has some length, so it has some inductance in series. It has a big area, like the top plate of a capacitor, so it has some capacitance to ground. You can reduce the capacitance by using a mitered bend.

It is interesting to look at the current distribution in EM analysis. Nearly all the current takes the inside path. I call this the Indy Effect, after the auto race, the race cars all take the inside of the track on a turn. Such a constriction of current further increases the inductance...and loss.

The comment above on paying attention to the ground return path is very very important. I have seen RFICs on silicon designed without any ground plane or ground strips of any kind. However, Maxwell will not be denied. The ground return was through the lossy silicon substrate. "Like..duh...where is all the extra loss coming from???" The ground return path can add loss as well as inductance!
 

wusen

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Besides the right-angle bends in the microstrip line, there are many forms of microstrip discontinuities, like open ends, gaps, slots, steps in width, T junctions, crossjunctions, and so on. In many cases, these discontinuities play a key role in the microstrip circuit design, not just "a grain of sand".

In my opinion, the essential characteristic of these discontinuities should be understanded by the disturbance of field or current, and can be modeled by lumped element equivalent circuits because the discontinuity dimensions are usually much smaller than the wavelength.

Your opinion is no fault yet, but it cann't express the question directly and will be difficulty to describe some discontinuities. How to evaluation that loop is increased in size? Is it the length of the current path or the increase of the phase? Here is an example of gaps, how can you express in the loop theory?
 

biff44

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I am with wusen on this one. Any discontinuity creates evanescent modes. These are places for energy to be stored but not dissipated. If there are no other discontinuities around for some distance, the energy in these evanescent modes eventually recombines into the main mode, and can be approximated by a lumped capacitance or inductance (sometimes negative ones).

What messes this all up is when you measure a discontinuity, like a microstrip bend, figure out equivalent lumped model to predict its behavior, and then screw up the model by putting another microstrip discontinuity too close to to the first one so that the evanescent modes have not mostly recombined yet. The original model is not longer valid in that case.

Added after 4 minutes:

ANd yes, sometimes there is some intuitive validity to the models. In a microstrip right angle, un-mitred, bend the currents tend to crowd closest to the inside of the bend, looking like a series pair of inductors. But the sharp outer point of the bend looks like a place for Efield concentration, suggesting a shunt capacitor. Hence the model, series L, shunt C, series L.
 

rautio

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Just for jokes, I did a bend in SonnetLite (I work for Sonnet). SonnetLite is free from http://www.sonnetsoftware.com, no time limit, problem size limited to 16 MBytes, 4 ports and 3 dielectrics. Packed project file is attached. Either unzip it, or change the extension to .zon and do File->Import in SonnetLite.

The bend is 0.75mm wide on input and 1.0mm wide on output, on 0.635mm Alumina substrate. Current distribution at 4 GHz is attached. Note current goes to the inside of the bend as expected. Zero current at the sharp corner means there is very high E-field there, as suggested above.

SonnetLite has an option to synthesize a lumped SPICE model for structures that are small with respect to wavelength. Read Chpt 22 in the user's manual (included in the SonnetLite download) for details. Briefly, it takes data at two frequencies and synthesizes the RLC combination that matches the data at those frequencies. If the lumped model is valid, you will get the same lumped model if you synthesize at two more frequencies. Be careful here because lumped models are limited in validity. Don't go prancing off with a bad model! Technical details in J. C. Rautio, "Synthesis of Lumped Models from N-Port Scattering Parameter Data," IEEE Tran. Microwave Theory Tech., Vol. 42, No. 3, March 1994, pp. 535-537 available from IEEE Explore, or I will email a pdf on request. Result (in PSPICE format) is:

* Sonnet Data File
* From: em Version : 10.52
* From Project: SimpleBend
* Data File Written: 02/22/2005 15:22:33
* < HDATE 02/22/2005 15:16:11
* < MDATE 02/22/2005 15:22:24
* Spice Data
* Limits: C>0.01pF L<100.0nH R<1000.0Ohms K>0.01
* Analysis frequencies: 2000.0, 3000.0 MHz
.subckt SimpleBend_0 1 2 GND
C_C1 1 GND 0.034582pf
C_C2 1 2 0.57792pf
C_C3 2 GND 0.136983pf
L_L1 1 2 0.077828nh
.ends SimpleBend_0

* Analysis frequencies: 3000.0, 4000.0 MHz
.subckt SimpleBend_1 1 2 GND
C_C1 1 GND 0.036716pf
C_C2 1 2 0.565649pf
C_C3 2 GND 0.139006pf
L_L1 1 2 0.077852nh
.ends SimpleBend_1

Looking at the differences between the two SPICE models, we can guess that the models are accurate to about 3% or so up to 4 GHz (the highest frequency analyzed for this example).

Note that all is as expected except...the port 1 to 2 connection is a parallel LC, not just an L. Interesting! As to why this is, it is undoubtedly due to the interaction of evanescent fringing fields as discussed above in this thread, but a more complete justification specific to this particular geometry I will leave to discussion. (i.e., I don't know why!)
 

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