Increasing FPGA clock frequency

[Ahmed Ragab]

clock frequency fpga faster

I've been reading through quicklogic's application notes and I found this:

Provide a slow clock on the board, and use built-in PLLs in intelligent devices to recreate a faster clock internally.
Clock signals have the highest switching activity, so the system clock frequency has a dramatic impact on the overall power consumption of a board. However, the clock speed also closely relates to bandwidth performance. To obtain the best balance between power and throughput, provide a slower clock to components that cannot benefit from having a fast clock. For devices that are critical to bandwidth, provide a fast clock, or use a built-in PLL (when available) to internally generate a fast clock within the device.
The QuickLogic μWatt FPGAs offers four built-in PLLs per device, so they can take slow clock inputs and generate fast clocks for internal or external usage. The μWatt FPGAs also offer embedded RAM blocks and clock routing resources, enabling time-domain crossings between multiple clocks.

Could someone explain more about PLL's and tell me how to utilize them in my design ? Any links or books concerning the topic are appreciated.

Salam.
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Ahmad M. Ragab