increase no'of multipliers vs VDD

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circuitking

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If I increase the number of multipliers term in a transistor,show I also increase VDD that many times? or is it going to taken care? because all the transistors are in parallel and they all going to have same VDD
 
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Are you referring to a signal amplifier with multi stage transistors ? What should actually be done is an analysis of the whole power dissipated against the power delivered on output, or in other words, to calculate the efficiency of the system. There is no generic answer, but in general the last stage is what practically which determines that value.
 

As you did not post to the ASIC section, in addition to the question being not sufficient elaborated this led people to a wrong premise that you were referring to the design of analog circuits.

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circuitking said:
I am asking about the "multiplier" option in transistor properties in cadence.
Click to expand...

The multiplier (m) creates m parallel devices with the same properties. This has nothing to do with VDD.
Here an example for an m=3 NMOS. In the netlist shown as (e.g.) M<1:3>

 
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