inconsistent OSC 18F4550

[3BABY]

Hi Guys,

so after the need for speed ive had to crank my 18F4550 up to 40Mhz.. but this is when the problems start.. i have the uC executing a test loop that sets all the LED's on PORTB for one seccond via a delay (@40Mhz).. when i have the 40Mhz crystal connected it works for a couple cycles and then for some reason some cycles are longer than others and then the uC just hangs... like it has no clock, (like if you were to pull out the osc midway through a program) please see the below shot - disregard the names on the left, just look at channel 3 orange.. however when i run exactly the same program on the same uC not reflashed or anything ..with a 20Mhz osc there is no problem .. the uC does not hang.. (again please see below pic)..

this is all on a Mikroeletronika Easy PIC6 board.. it has 22pF caps connected to the osc.. could this be the problem? do i need to change the cap values?

any help would be much appreciated!!

**broken link removed**

**broken link removed**

 

[keith1200rs]

Your problems are not surprising as the chip only allows 24MHz or 25MHz external crystal maximum depending on if you have the PLL enabled.

Keith

 

[3BABY]

Your problems are not surprising as the chip only allows 24MHz or 25MHz external crystal maximum depending on if you have the PLL enabled.

Keith

Hi Keith,

thanks for the reply! i was under the impression the CPU could run at 48Mhz ?

 

[keith1200rs]

Hi Keith,

thanks for the reply! i was under the impression the CPU could run at 48Mhz ?

It can, but you need to use the 4x PLL and the maximum crystal is 24MHz so to run at 48MHz you would have to use a 12MHz crystal and 4x PLL. Or you could run it at 96MHz with a 24MHz crystal, for example.

Keith.

---------- Post added at 08:50 ---------- Previous post was at 08:47 ----------

Actually, looking at the data sheet I think you can only get 96MHz from a 4 MHz clock and then it is divided by 2 to give the 48MHz. It doesn't look like you can use 4x 24MHz to get the 96MHz.

Keith.

 

[3BABY]

It can, but you need to use the 4x PLL and the maximum crystal is 24MHz so to run at 48MHz you would have to use a 12MHz crystal and 4x PLL. Or you could run it at 96MHz with a 24MHz crystal, for example.

Keith.

---------- Post added at 08:50 ---------- Previous post was at 08:47 ----------

Actually, looking at the data sheet I think you can only get 96MHz from a 4 MHz clock and then it is divided by 2 to give the 48MHz. It doesn't look like you can use 4x 24MHz to get the 96MHz.

Keith.

ah i see.. but i cannot get the CONFIG correct.. i have connected a 10Mhz osc and used the below (my target is 40Mhz at the moment - my 1sec delay is made for 1sec at 40Mhz) :

CONFIG FOSC = HSPLL_HS

CONFIG PLLDIV = 4

but now my 1sec delay time on the Logic Analyzer is 1.33 secs?

 

[keith1200rs]

I don't know what compiler you or using or how you are generating your delay, but the delay instructions usually require you to set the clock frequency so it can calculate the loop counter - maybe that is not correct.

Keith.

 

[Kurenai_ryu]

dude! the internal PLL for the PIC18F4550 ONLY generates 96/2 MHz from an 4 MHz input!!!! but you can divide your actual oscilator to get this 4MHz so you can use a 4,8,16,20,24 MHz crystal, divide it (with CPUDIV) and get the 96/2 MHz

i don't recommend to put a 10MHZ and PLL...

 

[3BABY]

I don't know what compiler you or using or how you are generating your delay, but the delay instructions usually require you to set the clock frequency so it can calculate the loop counter - maybe that is not correct.

Keith.

dude! the internal PLL for the PIC18F4550 ONLY generates 96/2 MHz from an 4 MHz input!!!! but you can divide your actual oscilator to get this 4MHz so you can use a 4,8,16,20,24 MHz crystal, divide it (with CPUDIV) and get the 96/2 MHz

i don't recommend to put a 10MHZ and PLL...

Thanks for the replys guys, im using MPLAB and the delay was checked in SIM before i ran it on the uC.. anyways no with CPUDIV = 2 and a 4Mhz osc i have the uC running at 48Mhz.. what i dont understand is how a 4Mhz osc can produce 96Mhz through PLL.. ? how does PLL work?

cheers Guys!!

 

[keith1200rs]

This PIC is different to most other PICs that I have used where the PLL normally has a wider range of input frequency. This one only allows 4MHz and has a fixed PLL multiplier.

The PLL consists of a free running voltage controlled oscillator and divider. The divided clock is compared to the reference clock (4MHz in this case) and the control voltage of the oscillator adjusted until they are locked.

Keith

 

[3BABY]

This PIC is different to most other PICs that I have used where the PLL normally has a wider range of input frequency. This one only allows 4MHz and has a fixed PLL multiplier.

The PLL consists of a free running voltage controlled oscillator and divider. The divided clock is compared to the reference clock (4MHz in this case) and the control voltage of the oscillator adjusted until they are locked.

Keith

Thanks Keith,.. ill have todo a bit of homework on the topic i think.. on another note.. have you (or anyone for that matter) seen a soft core for the PIC 18F series? ive had a look through open-cores but nothing exists there yet.. im thinking maby to get something around the 200Mhz mark it may have to be a core implemented in HDL.. whats your opinion?