Inconsistent behavior of MOSFET gate-driver

[med.setti]

Hello,

I am working on a 7-level power micro-inverter which composed mainly by power MOSFETs. These logic-level MOSFETs (IRLZ24NS) are driven by separate photovoltaic gate drivers with integrated fast turn-off (Broadcom ACPL-K30T). The problem comes when I try to simulate the circuit and compare the results with those obtained by experiments. The circuit topology with relevant signals looks like this:

As you can see, the gate-to-source voltage of the MOSFET M11 (V(g)-V(s)) at time starting from 11.68ms should be near to zero volts and not 2.31V, because the charge of the parasitic capacitors (Cgd and Cgs) will be discharged through the gate driver circuitry. This assertion was verified by breadboarding and gives the following result:

Noting that during my experiment I was using available Panasonic AVP1122 gate drivers instead of Broadcom ACPL-K30T which has comparative capabilities. However, I guess that problem comes from the ACPL-K30T SPICE model itself, I've tried to decipher it but didn't succeed, so I ask you SPICE gurus to help me understand the reasons behind this issue. The SPICE code is given below:

* ACPL-K30T  Spice Macromodel
.subckt ACPL-K30T AN CA VOUT- VOUT+
E1 N002 CA N014 N016 {CTR}
XX1 AN CA N016 N014 vbu
XX2 N002 CA N017 N015 pdnoc
XX3 N002 CA N008 N017 pdnoc
XX4 N002 CA N015 N013 pdnoc
XX5 N002 CA N013 N012 pdnoc
XX6 N002 CA N012 N010 pdnoc
XX7 N002 CA N010 N007 pdnoc
XX8 N002 CA N007 N004 pdnoc
XX9 N002 CA N004 N003 pdnoc
XX10 N002 CA N003 P001 pdnoc
XX11 N002 CA P002 P003 pdnoc
E2 N011 VOUT- N008 N001 1
R2 N009 N011 1k
D1 VOUT- N001 D
D2 N008 VOUT+ D
E3 N009 N006 N008 VOUT- 1
Q1 VOUT+ N006 N005 0 NPN
R3 VOUT- N005 3k
C1 VOUT- N009 37n
XX12 N002 CA P003 N001 pdnoc
XX13 N002 CA P001 P002 pdnoc
C2 VOUT- VOUT+ 100p
.param CTR=0.083
.ends ACPL-K30T

.subckt vbu AN CA LOPN LOPP
RSERIES AN 5 5
DELECT 5 CA VBUNOR
ELED 6 LOPN 5 CA 1
DOPTIC 6 8 VBUNORC
FPHOTO LOPN 3 VSENSE 1
VSENSE 8 LOPN 0
RL 3 LOPN 0.1
EOUT LOPP LOPN 3 LOPN 60
VSIM LOPN CA 0
Rnl 6 N001 5k
Vnl N002 LOPN 0
Fnl LOPN LOPN Vnl 1
Dsw N001 N002 DSW
.model DSW D Is=1e-4
.model VBUNOR D IS=330E-21 N=1.5 XTI=3 EG=1.52 BV=10.38 IBV=100u
+  CJO=60p VJ=.75 M=.3333 FC=.5 TT=20n
.model VBUNORC D IS=330E-21 N=1.5 XTI=3 EG=1.52 BV=10.38 IBV=100u
+  CJO=0 VJ=.75 M=.3333 FC=.5 TT=0
.ends vbu

.subckt pdnoc LOPP LOPN AN CA
D1 AN CA PDC
G1 CA AN LOPP LOPN 0.0010
.model PDC D IS=1E-14 N=1.5 CJO=0p M=0.95 VJ=0.75 ISR=100.0E-12 BV=100 TT=5E-9
.ends pdnoc

.model D D
.model NPN NPN
.model PNP PNP

Thank you

 

[Audioguru]

Your images do not open.
Post the images here (attach files) , not at Filebin that does not work.

 

[med.setti]

Your images do not open.
Post the images here (attach files) , not at Filebin that does not work.

Strange I see the images from my desktop and also thru my phone ! You find attached the requested images

 

[dick_freebird]

Those models' params look like fake, recommend you look at the driver operation more closely for match to datasheet (or the lack). Also appears you need to set the value of "CTR" param / arg to the first subckt.

 

[med.setti]

Those models' params look like fake, recommend you look at the driver operation more closely for match to datasheet (or the lack). Also appears you need to set the value of "CTR" param / arg to the first subckt.

The current transfer ratio or CTR has already been defined as .param CTR=0.083. But I think resetting this value doesn't solve the issue. The problem comes surely from the turn off circuitry which is unable to clamp the gate voltage to zero under off state due to the parasitic Miller capacitance Cgd

 

[cupoftea]

Cgs should be quite a bit bigger than cds to stop such spurious turn-on...try increasing cgs.
Photovoltaic fet drivers, i believe are not to be used in switching circuits....they have very very weak turn on drive...and dont actually have a turn off drive(?).
You should use bootstrap drivers, or 1EDI20N or digital isolator up to hi side gate drive supply, or pulse transformer....or one of the many drivers given by analog.com or infineon.com

 

[med.setti]

Cgs should be quite a bit bigger than cds to stop such spurious turn-on...try increasing cgs.
Photovoltaic fet drivers, i believe are not to be used in switching circuits....they have very very weak turn on drive...and dont actually have a turn off drive(?).
You should use bootstrap drivers, or 1EDI20N or digital isolator up to hi side gate drive supply, or pulse transformer....or one of the many drivers given by analog.com or infineon.com

Multilevel power inverters require a large number of power switches which most of them are in high side mode so optocouplers drivers with individual power supplies or complex bootstrap drivers are needed. On the contrary pv gate drives (or pv relays) do not require additional power supplies but can be used to switch small power MOSFET with low Qg.

 

[KlausST]

Hi,

You say bootstrap drivers are complex. I call them rather simple. In simplest case a capacitor and a diode.
They are used many million times... proven ... ready to buy ICs...

Klaus

 

[med.setti]

Hi,

You say bootstrap drivers are complex. I call them rather simple. In simplest case a capacitor and a diode.
They are used many million times... proven ... ready to buy ICs...

Klaus

Yes I agree the technique is intrinsically simple but would become complex due to the large number of power switch to drive.

 

[BradtheRad]

Your circuit appears to have several H-bridges switching 12V batteries in ones & twos & threes. You achieve this with a sophisticated gating scheme and three batteries. A clever method.

Typical multi-level diode-clamped converter schematics use a simpler topology and gating scheme. Below is a simulation with analog-switches (which is cheating but merely to demonstrate the concept).

It's not necessarily more efficient than your method.

This isn't diode-clamped although it has diodes/led's in vital locations. It uses six 12v batteries. My snapshot was taken when all three positive polarities are conducting. The switches turn on in sequence, then Off in sequence. By overlapping On-times it minimizes glitchy spikes.

To build this via switching mosfets is extra effort. Choices are whether to place N or P devices, whether in the positive section or negative section, how to bias.
Also what value resistors to attach at bias terminals. These are pull-up or pulldown resistors to create default Off or On state.

Then configure the op amps to apply hi or low bias voltage, to turn mosfets On and Off. Etc. By this method the op amps can all deliver either 12V or 0V. I reworked my simulation in an effort to get everything right. It's almost within reach although I'm finding it's a headache.