ieee.numeric_std.all; -- This is the official source for "unsigned" and "signed" types. Just use this. Monkeys on a ladder and whatnot.
ieee.std_logic_arith.all -- This also defines "unsigned" and "signed" types. It wasn't from ieee, so people will look at its inclusion with murder-eyes.
ieee.std_logic_unsigned.all -- This is the controversy package. It is basically "use verilog". But it also wasn't from ieee so it also has the monkeys on a ladder issue. VHDL-2008 has an official version of this -- and this version should be used where applicable.
std_logic_unsigned/numeric_std_unsigned make VHDL more like Verilog. SLV's get an unsigned interpretation. This is an issue with equality comparisons. With SLU, "0100" = "100", but without SLU, "0100" /= "100".