In STA clock uncertainty value problem

[archillios]

hold uncertainty

hi guys, I often see the following STA constraints:
set_clock_uncertainty 200ps -setup
set_clock_uncertainty 100ps -hold

Why the value use in setup checking is set bigger than the value used in hold checking?

Thanks!

 

[ljxpjpjljx]

clock uncertainty

because it depends on you clock!

 

[dcreddy1980]

sta jitter margin

Hi,

You would see these constraints before place and route, before we have a clock tree for the specified block. Adding more uncertainity to the setup part is over-constraining the block, This could be done by running the block at higher frequency i.e 10% more than u r target frequency(Just an example, percentage depends up on the designer). Over-constraining the block sometimes may not fetch desired results.

Regards,
dcreddy

 

[rhythmrain]

clock hold uncertainty

hi guys, I often see the following STA constraints:
set_clock_uncertainty 200ps -setup
set_clock_uncertainty 100ps -hold

Why the value use in setup checking is set bigger than the value used in hold checking?

Thanks!

1) to make chip run faster as specified in real silicon, we need more margin for setup in STA
2) the source of uncertainty include : PLL jitter, clock skew(before CTS), OCV (before post-routing), guard margin.
setup uncertainty should include all of them. but we can ignore PLL jitter in hold uncertainty, and OCV uncertainty for hold can less than setup.

Anyway, hold uncertainty always less than setup uncertainty in STA.

 

[archillios]

uncertainty value

Thank you guys, I got some understanding from your discussion.