In L=180nm, for 2GHz Fref, how to design frequency divider using static DFF?

[Eddison]

I want to make Frequency Divider as Fref/4.
If I can use static DFF in low jitter(30f) and low power(2mW) condition,
I want to design it.
However, after many different sizing in schematic simulation, I can't match provided condition.
If I increase width size of CMOS tr in 3-NAND gate, power increases.
If I increase length size of CMOS tr, power and jitter increases.
I tried PMOS width as 2~4 times of NMOS width.
The cause of jitter is mainly from fliker noise.
If the condition is hard, then is 1GHz -> 500MHz static DFF possible?
In L=180nm, for 2GHz Fref, which DFF would I select either static or dynamic?
Thank you for reading.

 

[erikl]

May be this thread might be helpful: frequency division by CurrentModeLogic:

 

[dick_freebird]

In "bang bang CMOS" this is pretty unlikely. A dynamic
DFF (CMOS) or a differential low swing high speed
style (as above) is the norm in CMOS RFIC prescalers
at these submicron (not deep) nodes. Even FDSOI at
these Ls is probably incapable of robust operation at
2GHz, maybe the second stage (maybe).

If you think you've succeeded, add parasitics and look
again.

 

[Eddison]

Thank you for helping me. Maybe it is better to design it using dynamic DFF. Hope to have a nice day