In gate-level simulation, how to set stimulus with respect to PLL generated clk?

[nervecell_23]

Hi,

I have a design which contains a PLL that generates system clk.
Now I want to do gate-level simulation for that design. Since some of the stimulus in the testbench are with respect to the system clk (The testbench only generates reference clk for the design), I wonder how to capture the system clk generated by PLL?

If I simply set up another clk with the same frequency as the system clk in the testbench, will it work? (I'm not sure whether the rising edge of this clk will be in alignment with the system clk)

Thanks!

 

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If stimulus in the testbench are with respect to the system clock then it seems to me the system design needs some work.

An internal clock generated off a PLL shouldn't be used for signals outside the chip, unless you generate a system clock from the FPGA that runs the rest of the system or you are using a zero delay setting for the PLL to remove the clock insertion. Even then you should have constraints on the I/O to address the timing between the internal system clock and the external version of system clock.