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firstly, since there is no gate volage channel will not be there so no current will flow and the device will be in cut-off with a -ve substrate(as it is nmos all holes will be attracted by the -ve substrate voltage, and reversed biased pn junction diode so no current flows)
now increasing the subtrate voltage to a +ve side result in a small diode current(drain and substrate form a forward biased pn junction diode) but the transistor will be cutoff.