In a 2-input NAND, which will be faster when switching: when the A input turns on first, or B?

[jktstance]

On the image below, if Vout is initially Vdd and A and B are 0, will the gate delay and slew be less if A switches to 1 before B, or vice versa?

I believe the answer is B before A, because if A turns on before B, then the source of A will be pulled up to Vdd, and then pulled down when B opens up. However, I can't really convince myself of that, because why does it matter if Vds of the bottom transistor is Vdd? It will still have to drain 5V. If B turns on first, then the drain of the top nmos will be pulled down to 0, so the top nmos will still have to drain 5V. What am I missing here?

--- Updated Aug 27, 2020 ---

This was an interview question I somehow got right, but I still can't convince myself. I believe the interviewer was assuming the A or B transistor will be fully switched on or off before the other one is enabled, in which case my above question still stands.

If they are not fully on and drain all of Vds before the next one does, then I can imagine B before A being correct because if B conducts first, it is pulling the source of A down, and then when A conducts after it will pull down Vout. If A conducts first, then the drain of B will be pulled up towards Vdd, and then down when B turns on after.

 

[vGoodtimes]

Isn't it A first? If A is held high, doesn't the lower transistor connect the switching output to extra capacitance?

 

[jktstance]

I thought about that too. If we assume A or B fully turn on before the other one does, my thought process is this (I don't know if it's correct).

If A turns on first, then the source of A is pulled up to Vdd and the intrinsic capacitance of A is fully charged. When B turns on later, Vout and the potential of the A capacitance all have to be discharged through B.

If B closes first, then the drain (or source of A) is pulled down to 0. Then when A closes, Vout needs to discharge through both, but it does not need to discharge Vdd potential in A's capacitance like it did above.

So I'm thinking of full electric charge as the limiting factor. I don't know if this is the correct way to look at this, but I was hoping for a solid answer as to why it was B before A (I'm almost positive the interview said that was the case, and it was because 0 gets propagated up through B first.