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Dd you mean reduce the number of patterns with the same coverage?
If yes, used testkompress, added fault covered by none atpg test, like Bist, analog tests...
Dont try to reduce DFT cost. Your goal is to reduce the total lifetime IC cost and sometimes that means increasing DFT cost.
Catch a defect at wafer probe and you have lost the cost of one die. If it slips through and the customer catches it then the
cost goes up about 2 orders of magnitude.
I agree with you, but in new chips there are utilization problems and cell count amount , so there is a reasonable need to reduce cell count - by reduce dft cell count ot remove some features. thats why I ask you for ideas to decrease DFT size.
I agree with you, but in new chips there are utilization problems and cell count amount , so there is a reasonable need to reduce cell count - by reduce dft cell count ot remove some features. thats why I ask you for ideas to decrease DFT size.
There are some other research Scan Architecture which are occupies less area and power means less extra Hardware for DFT. But those are not implemented by any EDA tool for inserting in the Design. So that is not practically possible as EDA tool not supported.
But present Scan architecture, if we reduce anything related to DFT, thn we have a loss of test and fault coverage.
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