Thanks a lot. The only problem is I don't have CST Design Studio. I've used Ansoft Designer and HFSS so far, and I'm a beginner with CST MWS. I did the same with HFSS and Designer, but I have problems in setting boundaries with this kind of structure.
It is a unit cell of an infinite array. A vertically polarized plane wave should excite a current in the receiving folded slot. Then, the FET amplifies the excited current towards the drain. Finally, the re-transmitting orthogonal folded slot must reradiate the amplified signal, which is orthogonally polarized with respect to the incident field. I know I have to use periodic boundaries (Master-slave in HFSS, periodic in CST) and floquet ports, but results are totally unreliable, probably because of boundaries and port settings. My intention is to get a 4 port S-matrix (input free space, output free space, FET gate lumped port, FET drain lumped port) in Designer in order to get the gain (s21) of a unit cell embedded into an infinite array. Any idea of how to do that, considering both the passive structure and the active device? How to set correct boundaries and free space ports?
Thanks again.
Ivan