risc
Newbie level 4
xilinx import ngc
Hi,
Does anyone know how to import the EDN/NGC netlist file to a VHDL project in Xilinx ISE tool in order to reduce design time?
I used to use this method in Altera with VQM netlist files with LogicLock feature. But I did not find any similar way to do that in Xilinx ISE tool.
Could anyone give me some suggestion?
Thnks
Hi,
Does anyone know how to import the EDN/NGC netlist file to a VHDL project in Xilinx ISE tool in order to reduce design time?
I used to use this method in Altera with VQM netlist files with LogicLock feature. But I did not find any similar way to do that in Xilinx ISE tool.
Could anyone give me some suggestion?
Thnks