Implementing JTAG cable from Xilinx for CPLD

[swapnil_vlsi]

HI,

can tell me about JTAG Cable.i hav to download a code to CPLD using JTAG Cable.i implemented the JTAG Cable from Xilinx site ........
is there any difference between JTAG for FPGA n CPLD...........
WHAT DIFFERENT HARDWARE FOR CPLD....

WHILE downloading it shows a id code error not matched with expected code ...
asking for BSDL file ....already there is .jed file is generated ?
...... where i get wrong can any one tell me?

 

[madhavisai]

jtag 74hc125

if u r getting that error just swich of the kit once n switch on and assign .bit pattern again

 

[banjo]

jtag cable for cpld xc9572

By implementing the Xilinx cable from the website, I am assuming that you built the 74HC125 circuit shown on the web. A couple of things to check. This is the same circuit Xilinx sells in their Parallel Port III adapter. Lots of people have built this and gotten it to work, so the design is solid.

A: The circuit MUST get its power from the CPLD host. Verify that 3-5V from pin 14 to 7 of the 74HC125. No power means no work.

B: The Impact software has a quirk in that if you attempt to access a CPLD or FPGA without powering up the device, the software will go into a bad state and will refuse to work even after you correct the power problem. The solution is to exit Impact and restart it. Also, be careful not to click the icon too many times. The program is slow to show a splash screen. If you click it again, it launches two copies and they will fight each other for control. Best method is to connect cable, power up the board, and then launch Impact.

C: Later versions of Impact have a debug mode that you can use to toggle TCK, TMS and TDI. This this is helpful in checking out your circuit connections. Look through the menus on the top banner and try using the debug mode. To describe JTAG in a couple of sentences. TCK is the clock. TMS is a signal used to differentiate between data and commands. TDI is a data into the CPLD or FPGA. TDO is data from the CPLD or FPGA back to the programmer. TCK and TDI toggle quite often. TMS toggles less frequently. TDO only toggles when the part is giving back data. TDO is open drain and must have an external pullup to VCC (see schematic).

D: This circuit ONLY works with a parallel ports that are connected to the motherboard or a plugin PCI card. It does NOT work with USB to parallel port converters.

E: Parallel port settings in BIOS can affect operation on some computers. If all else fails, try changing the BIOS settings.

F: Intermittent failures are possible in Windows XP. The problem is that XP periodically polls the ports looking for new Plug and Play devices. If XP polls the port during the time you are using it, failures can occur.

---- Steve

 

[muralicrl]

jtag cable schematic 74hc125

Hello,

What is the VCC level of your CPLD. Because if the VCC levels are different like 3.3V or 5V, there has to be different cable you may have to use.
Please tell me the Part name of your CPLD.

If u need more info don't hesitate to ask me.

Thank you,
N.Muralidhara

 

[shashialabur]

how to use jtag download to cpld xilinx

Hi

I am going to use the XC9572 device for the first time.

I have the required JED file and I just need to program the XC9572 device using the JTAG port on my board.

I will make the parallel port programming adapter using the 74HC125 IC as per the pdf document posted on the web and in another post on this forum.

What software do I need to run to program this device on my PC ?

All the links on the Xilinx website end up with software suites which are 900MB or larger ! Isn't there a simple program only software ?

Thanks !

 

[mosi]

how to down load cpld by jtag

Hi
You can use Xilinx ISE Webpack Edition
or
Use older version of Xilinx ISE Foundation ....

 

[shashialabur]

tms cpld

Hi Mosi,

Do you have any links where I can get a smaller file size to download ? The ISE Webpack or the Foundation are 900MB downloads !

I only want to program the CPLD - that too only XC9572 device - and not really do the entire design process for the whole family of Xilinx devices.

If I have no choice but to download such a large file, then I will have to do it, I suppose !

Thanks
Shashi

 

[kvingle]

what is 74hc125

You can select individual files to download ...and then select only standalone programming tools on xilinx..

Or download web installer (around 48 mb) of ISE.
Then select only programming tool option while installation.



Well sadly that also has a filesize of 651 MB.

 

[shashialabur]

parallel port settings for jtag to work

Thanks for all the help guys !

Made the programming adapter as per the schematics posted on this forum, downloaded the 650MB ISE Webpack from Xilinx and everything worked like a charm to program the Xilinx devices on board !!